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Input block remapping FFT method based on FPGA
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A remapping and block technology, which is applied in the field of FFT operation speed optimization on the FPGA platform, can solve the problems of slow FFT operation speed and no FPGA internal resource utilization.
Inactive Publication Date: 2021-09-17
HARBIN INST OF TECH
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[0004] The purpose of the present invention is to solve the problem that the FFT operation speed is slow in the existing method, and the internal resources of the FPGA are not maximized, and a FPGA-based input block remapping FFT method is proposed
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specific Embodiment approach 1
[0021] Specific implementation mode 1. Combination figure 1 This embodiment will be described. A kind of FPGA-based input block remapping FFT method described in the present embodiment, described method comprises data input remapping module, butterfly computing network module, data output module, wherein:
[0022] The data input remapping module is used to optimize the input data into a data flow format of parallel blocks, that is, output parallel block data through the data input remapping module;
[0023] The butterfly computing network module includes several FFT butterfly networks;
[0024] The data input remapping module maps the parallel block data to the corresponding FFT butterfly network according to the designed output sequence;
[0026] The data output module is used to output the discrete Fourier transf...
specific Embodiment approach 2
[0031] Embodiment 2: The difference between this embodiment and Embodiment 1 is that when the data input remapping module optimizes the input data, it executes L times the throughput of the data stream, where L is the number of parallel outputs of the ADC .
[0032] Other steps and parameters are the same as those in Embodiment 1.
specific Embodiment approach 3
[0033] Specific embodiment three: the difference between this embodiment and specific embodiment one or two is that the data input remapping module and the data output module are packaged as a RAM communication interface on the FPGA;
[0035] The input data size of the data input remapping module is 1*32, wherein, 8 are divided into one group and carry out parallel input;
[0036] The butterfly operation network module includes log 2 N FFT butterfly networks, where N is the number of FFT calculation points;
[0037] In the butterfly operation network module, after the input data of the i-th FFT butterfly network is input, the data dimension remains unchanged, and the calculation interval of the output data is 2 i , i=1,2,...,log 2 N.
[0038] The butterfly calculation network module includes the structuring of parameters such as the size of the twiddle factor calculation, the programming o...
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Abstract
The invention discloses an input block remapping FFT method based on an FPGA, and belongs to the technical field of FFT operation speed optimization on an FPGA platform. The problems that in an existing method, the FFT operation speed is low, and FPGA internal resources are not utilized to the maximum degree are solved. According to the invention, a butterfly algorithm with an improved input structure is used, starting from the calculation process of FFT and the hardware architecture of an FPGA, an HLS compiling tool is adopted to input data in parallel input FFT operation into a remapping module and initialize a butterfly operation coefficient into an IP core, and integration with hardware is achieved. According to the FFT method designed by the invention, FFT calculation can be carried out on parallel input data on an FPGA platform, the operation efficiency of FFT carried out on parallel interpolation input signals on the FPGA platform is maximized, the time performance is superior to that of an official IP core, and maximum utilization of FPGA internal resources is realized. The invention can be applied to optimization of the FFT operation speed on the FPGA platform.
Description
technical field [0001] The invention belongs to the field of FFT operation speed optimization on an FPGA platform, and in particular relates to an FPGA-based input block remapping FFT (fast Fourier transform, fast Fourier transform) method. Background technique [0002] Ultra-high-speed (Gsps) AD converters can be widely used in wireless communication, software radio, data acquisition, optical communication, instrumentation and other fields. FPGA logic typically cannot keep up with the bus speeds of high-speed ADCs, so most FPGAs have serializer / deserializer (SERDES) blocks to convert the fast, narrowband serial interface on the converter side to the slow, narrowband serial interface on the FPGA side. Broadband parallel interface. In the system platform integrated with high-speed ADC and FPGA, there are usually related signalprocessing algorithms, and these algorithms often need to be improved to ensure the maximum efficiency after being implemented on a specific platform....
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