High-voltage plane gate MOS device with groove structure and processing technology of high-voltage plane gate MOS device
A technology of MOS devices and planar gates, applied in semiconductor devices, semiconductor/solid-state device manufacturing, electrical components, etc. On-resistance, the effect of increasing the breakdown voltage
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Embodiment 1
[0055] figure 1 It is a schematic cross-sectional structure diagram of a high-voltage planar gate MOS device with a trench structure according to an exemplary embodiment. Such as figure 1 As shown, a high-voltage planar gate MOS device with a trench structure provided by an embodiment of the present invention includes a drain region 1 of the first conductivity type located at the bottom of the MOS device and a first conductive type extending upward from the upper surface of the drain region 1 . An epitaxial layer 2 of conductivity type, a trench 3 with an upward opening is arranged on the epitaxial layer 2, a gate oxide layer 4 is disposed in the trench 3 and on the surface of the epitaxial layer 2, and polysilicon is disposed above the gate oxide layer 4 layer 5, a source region 6 is arranged on the top of the epitaxial layer 2, and the upper surface of the source region 6 is flush with the upper surface of the epitaxial layer 2 and is in contact with the gate oxide layer 4;...
Embodiment 2
[0097] The difference between this embodiment and embodiment 1 is: as Figure 15 As shown, the thickness of the gate oxide layer at the bottom of the trench is greater than the thickness of the gate oxide layer at the side of the trench and above the epitaxial layer, which can reduce the electric field intensity at the corner of the bottom of the trench, improve device reliability, and reduce gate leakage. capacitance.
[0098] In this embodiment, the thickness of the gate oxide layer 4 located above the top of the epitaxial layer 2 of the first conductivity type is the same as the thickness of the portion located on the inner side of the trench 3, both being 90 nm, and located at the bottom of the trench. The thickness of the gate oxide layer is greater than 1.5μm.
[0099] In its processing process, after etching the trench, deposit silicon dioxide to fill the trench, and then etch back the silicon dioxide. The thickness of the remaining silicon dioxide in the trench should...
Embodiment 3
[0101] The difference between this embodiment and embodiment 1 is: as Figure 16 As shown, the center of the bottom of the trench 3 is depressed downwards, that is, the corners of the bottom of the trench are etched into a circular arc shape, thereby reducing the electric field intensity at the corners of the bottom of the trench and improving device reliability.
[0102] In this embodiment, the gate oxide layer 4 has a thickness of 90 nm at all locations.
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Abstract
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