Transistor with local bottom gate and manufacturing method thereof

Abstract

The invention relates to a transistor with a local bottom gate and a manufacturing method of the transistor. The transistor comprises a substrate, a low-dimensional semiconductor layer, a source electrode, a drain electrode and the local bottom gate; the local bottom gate is located on the substrate, a gate dielectric layer is arranged on the local bottom gate, the low-dimensional semiconductor layer is located on the gate dielectric layer to serve as a channel of a transistor device, the source electrode and the drain electrode are located on the two opposite sides of the low-dimensional semiconductor channel and make contact with one or more parts of the low-dimensional semiconductor layer respectively; a transition layer and an electrostatic doping layer are arranged on the source electrode, the drain electrode and the channel layer, and fixed charges are arranged in the electrostatic doping layer, so that electrostatic doping is carried out on the corresponding low-dimensional semiconductor channel layer to form an NMOS device, and meanwhile, the invention also provides a manufacturing method of the transistor. The transistor provided by the invention has the advantages of good thermal stability, accurate and controllable threshold voltage and compatibility in process, and can meet the requirements of large-scale carbon-based integrated circuit production.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a transistor with a partial bottom gate and a preparation method thereof. Background technique [0002] Low-dimensional semiconductor materials, such as carbon nanotubes, graphene, black phosphorus, or two-dimensional materials, are widely used due to their excellent properties such as thin thickness, high mobility, high physical and chemical stability, and high thermal conductivity. Used as a channel material in transistors. Similar to the traditional semiconductor process, transistors with low-dimensional materials as the channel can also change the distribution of carriers in the semiconductor channel material by doping the low-dimensional material, thereby changing its electrical properties and forming p-type regions respectively And n-type regions, and then form semiconductor devices with various structural functions, such as diodes, field effect transistors, etc. Howe...

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Problems solved by technology

However, there are still many problems in the low-dimensional material transistors prepared by the above two methods. Taking carbon nanotube transistors as an example, the threshold voltage of high-k dielectric transistors prepared by using metal materials with matching metal work functions to form the source and drain electrodes cannot be effectively adjusted. , the drain terminal is prone to reverse tunneling in the off state, causing problems such as a decrease in the switching ratio

Transistors prepared by using a local bottom gate combined with electrostatic doping on the channel surface, or a top gate structure using electrostatic doping of gate dielectric oxides, currently achieve electrostatic doping usually using incomplete metal oxides (that is, there are more Many oxygen vacancies or dangling bonds, etc.), the interface is unstable, and there are many defect states and interface states, which will reduce the channel mobility, which is not conducive to gate control, affect the uniformity of the device, and the process repeatability is poor.

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