66results about How to "Strong process compatibility" patented technology

The invention discloses a scaling powder for a nickel-plating alloy soft soldering tin wire core and the preparation method of the scaling powder. The weight formula of the scaling powder comprises the following components by weight percent: 60-90% of resin, 0.1-20% of organic acid, 0.1-10% of organic amine, 0.1-20% of metal salt, 0.1-2.0% of active strengthening agent, 0.1-2.0% of surfactant, 0.1-1.0% of corrosion inhibitor and 0.1-1.0% of antioxidant. The scaling powder disclosed by the invention is suitable for producing lead-containing or non-lead solder tin wire containing scaling powder and can be used for automatically welding or manually welding nickel-plate alloy; and when in use, the welding time of the tin wire is short, the wettability is good and the welding residues are few, so that the scaling powder belongs to environment-friendly scaling powder, and the tensile strength of the welding point joint is high and the insulating resistance is large. The tin wire prepared by the invention is very suitable for soft soldering of nickel-plate alloy and is suitable for soft soldering of chromium plating, gold plating, copper and copper alloy.

The invention relates to an array multiparameter wind sensor chip substrate and the making method thereof, relating to the wind sensor field. And it comprises a substrate, n heating components, m thermosensitive components and several heat insulation grooves, where n is natural number not less than 2, m=n+1, the substrate is a circular or regular polygonal nonconductive plate, n centrosymmetric heating components are fixed on the back of the substrate, a heat insulation groove is made between every two adjacent heating components, n thermosensitive components corresponding to the n heating components are fixed on the obverse side of the substrate, a thermosenstive component is fixed in the center of the obverse side of the substrate, and a heat insulation groove is made between every two adjacent thermosensitive components. And it can apply to wind sensors and wind parameter measuring systems.

A preparation method for improving the reliability of a semiconductor laser, which adopts one-time etching to simultaneously remove the ohmic contact layer other than the ridge-shaped mesa of the semiconductor laser, and introduces a non-implantation region window structure. The present invention is based on the Schottky contact principle between the P electrode and the epitaxial layer of the chip, and simultaneously removes the ohmic contact layer other than the ridge-shaped mesa and the ohmic contact layer at the cavity surface through a single etching process to introduce a non-implantation region window structure to form a Schottky The base contact layer achieves the purpose of preventing leakage on both sides of the double channel region in the laser, improving device reliability and increasing the COD threshold. The invention only adopts one-time photolithography process, has simple preparation process, wide application range and strong compatibility, and can be combined with other special processes to further improve the performance of semiconductor lasers.

The invention discloses a field effect transistor gas sensor and an array preparation method thereof. The field effect transistor (FET) gas sensor is a gate-sensitive FET gas sensor with a gate electrode modified by quantum dots, and a gate-sensitive electrode layer (5) of the FET gas sensor is of a two-layer composite structure or of a single-layer structure made of a composite material. The two-layer composite structure comprises a metal film layer and a quantum dot layer deposited on the surface of the metal film layer. The single-layer structure made of a composite material is specificallya single-layer structure made of a composite material formed by combining quantum dots and a metal or metalloid material. According to the invention, improvement is made on the internal composition and structure of the gate-sensitive FET, the corresponding preparation method and the like, quantum dots are used as a gate electrode and a gas sensitive layer at the same time, and the bias voltage ofthe gate electrode and the channel modulation effect are regulated and controlled by utilizing the adsorption characteristic of a quantum dot gate-sensitive electrode to different gases. A room-temperature gas sensor with high sensitivity, low power consumption and high selectivity can be obtained, and low-concentration target gases (such as H2) can be detected.

The invention discloses a GaAs substrate mHEMT active region electrical isolating method, which is a method combining wet etching and ion implantation for active region electrical isolation of a various-component high-electron-mobility transistor. The GaAs substrate mHEMT active region electrical isolating method comprises the steps of removing a surface highly-doped layer and then carrying out ion implantation isolation, thereby effectively improving the ion implantation effect, and further improving the isolation effect between active regions. Under the same condition, the isolating method combining ion implantation and mesa etching has the advantages of good electrical isolation effect, high process compatibility, small impact on subsequent process, good reproducibility, easy implementation and the like, effectively avoids the defects caused by adopting mesa etching and ion implantation separately, and has good use value for the semiconductor manufacturing process.

The invention discloses a soft nerve probe based on mixed silica gel and a preparation method of the soft nerve probe. The preparation method comprises the following steps: mixing two or more silica gel with different Young moduli, and doping silicone oil to obtain an elastic mixed silica gel substrate; a first polymer film is deposited on an elastic mixed silica gel substrate to serve as a bottom polymer insulating layer, and wrinkles are formed automatically; the metal conducting layer is located on the bottom polymer insulating layer, and a second polymer film is deposited on the metal conducting layer to serve as a top polymer packaging layer; the two layers of polymer films are etched into a snakelike line contour through oxygen plasma reaction etching, and the flexible nerve probe contour is obtained through laser cutting of the elastic mixed silica gel substrate. The device is suitable for low-damage implantation of probes with different lengths; the bonding force between the electroplating modified material and an electrode point interface can be effectively improved, the stability of a plating layer is improved, the bonding force between the electroplating electrode modified material and the electrode interface is also effectively improved, and stable and reliable electrochemical performance is ensured.

The invention provides a molybdenum disulfide photoelectric detector and a preparation method thereof. The molybdenum disulfide photoelectric detector comprises a metal reflecting layer, an insulating medium layer, a molybdenum disulfide layer, a source electrode and a drain electrode, wherein the metal reflecting layer, the insulating medium layer and the molybdenum disulfide layer are arranged from bottom to top, the source electrode and the drain electrode are arranged on the molybdenum disulfide layer at an interval, and the drain electrode comprises an electrode part and a grating part. According to the molybdenum disulfide photoelectric detector, the metal emission layer is adopted as the bottom layer, and the grating is integrated on the drain electrode, so that obvious light absorption difference can be formed between the drain electrode and the source electrode of the photoelectric detector, the symmetry of the light current at the two ends of the drain electrode and the source electrode is broken, and the light response of the photoelectric detector is enhanced.

The invention provides a metal interconnection structure and a manufacturing method thereof. The manufacturing method comprises the following steps of: manufacturing a metal interconnection structure on a substrate, wherein the metal interconnection structure comprises a metal wire pattern, a conductive plug and a medium layer which is filled between the metal wire pattern and the conductive plug; performing photoetching, and etching the metal interconnection structure by adopting an anisotropic dry etching method from top to bottom, and at least forming a through hole or a groove on an area which is a medium layer from top to bottom; and removing the medium layer below the metal wire pattern by adopting an isotropic removing method to form a novel metal interconnection structure, wherein the two ends of the novel metal interconnection structure are embedded into the medium layer, and other parts of the novel metal interconnection structure float in the groove or the hole. Due to the adoption of the technical scheme of the invention, certain requirements on a suspended metal interconnection structure can be met, e.g., non-matching conditions with a lens can be reduced, the light crosstalk phenomenon is reduced, and needed materials can be filled into a suspended structure.

The present invention discloses an ion implantation method capable of preventing a silicon edge on the boundary of an ion implantation region from peeling off. The method comprises the following steps of: firstly, performing processing on the surface of a silicon chip, so that an oxide layer is generated on the surface of the silicon chip; then coating the silicon chip with a photoresist; then performing ion implantation on the silicon chip; and finally removing the photoresist on the surface of the silicon chip. According to the present invention, by performing processing on the surface of the silicon chip, an ultrathin oxide layer is generated on the surface of the silicon chip to prevent the silicon chip from generating the silicon edge in the photoresist-removing process, thereby avoiding the silicon peeling problem, reducing surface defects and improving the rate of finished products.

The invention belongs to the technical field of battery materials. The invention provides a pre-sodium-modified positive pole piece. The pre-sodium-modified positive pole piece comprises high-voltage sodium ion positive pole slurry, high-capacity sodium ion positive pole slurry and a current collector, and the thickness of the high-voltage sodium ion positive electrode slurry is 10-15% of the sum of the thicknesses of the high-voltage sodium ion positive electrode slurry and the high-capacity sodium ion positive electrode slurry. Due to the effective use of the positive electrode sodium supplementing technology, the irreversible sodium loss of the hard carbon negative electrode is reduced, the dynamic performance of the sodium ion battery is improved, and the polarization is reduced; therefore, the high-performance sodium ion battery has the initial coulombic efficiency of more than 95%, the energy density of more than 150Wh/kg, the cycle life of more than 6000 weeks, the charge-discharge capacity at-40 DEG C and the continuous discharge capacity at 30C multiplying power, and the comprehensive electrochemical performance of the sodium ion battery is improved.

The invention provides a high-voltage IGBT device with a built-in ballast resistor. A cell structure includes a first conductivity type semiconductor P+ collector region, a metal collector, a second conductivity type semiconductor buffer layer, a second conductivity type semiconductor N-drift region, a first conductivity type semiconductor P type base region, a heavily doped first conductivity type semiconductor P+ doping region, a second conductivity type semiconductor built-in ballast resistance region, and a heavily doped second conductivity type semiconductor N+ emitter region. The secondconductivity type semiconductor built-in ballast resistance region is used for replacing the part, extending horizontally towards the space below the gate structure, of the second conductivity type semiconductor N+ emitter region, so that the second conductivity type semiconductor built-in ballast resistance region is located in the gate voltage control region. On the basis of the positive temperature characteristic of the ballast resistance value at a high temperature, the short-circuit capability of the device is improved; and the thermal stability of the device in the forward blocking stateis enhanced.

The invention provides an insulated gate bipolar transistor and a preparation method thereof. The insulated gate bipolar transistor comprises an N-drift region (4), P-type base regions (5), N-buffer layers (10) and N+emitter regions (6); the P-type base regions (5) are located on the two sides of the upper surface of the N-drift region (4), and the N+emitter regions (6) are located on the upper surfaces of the P-type base regions (5) and have a set distance away from the outer sides of the P-type base regions (5); and the N-buffer layers (10) are located in the P-type base regions (5) below the N+emitter regions (6), the conduction voltage drop of the insulated gate bipolar transistor is reduced through the N-buffer layers (10), and the latch-up phenomenon of the insulated gate bipolar transistor is effectively inhibited. According to the insulated gate bipolar transistor, the carrier concentration in the drift region is improved through Schottky contact, and the distribution of carriers in the drift region of the insulated gate bipolar transistor is further improved, so that the conductivity modulation effect is enhanced, the conduction voltage drop is reduced, the firmness of theinsulated gate bipolar transistor is improved through the N-buffer layers, and the large-current turn-off capability of the insulated gate bipolar transistor is improved.

The invention relates to realization method for the titanium silicide in CMOS technique, which comprises, first, injecting amorphous compound on CMOS with formed source/drain/grid; then, sputtering to deposit titan at normal temperature for CMOS and adding the sputter and deposit for titanium nitride; annealing quickly for the first time; wet etching by NH4OH/H2O2/H2O; finally, annealing quickly for the second time to form titanium silicide. This method restrains effectively the narrow channel effect, saves time and cost.

The invention provides an OLED product and a production method thereof. The production method comprises the following steps: 1, providing an ITO substrate; 2, etching a first ITO layer on the ITO substrate to form an ITO anode layer; 3, producing an Mo alloy layer on the ITO anode layer, and producing a second ITO layer on the other surface of the ITO substrate; 4, etching the second ITO layer toform a first ITO touch layer; 5, producing and etching a first Mo/Al/Mo pattern layer on the first ITO touch layer; 6, producing a hard protective layer on the first ITO touch layer and the first Mo/Al/Mo pattern layer; 7, removing the Mo alloy layer; 8, producing and etching a second Mo/Al/Mo pattern layer on the ITO anode layer; 9: producing an OLED functional layer and a metal cathode layer. Bythe production method, the problem of poor compatibility between the existing technical scheme of adding auxiliary metal in the process of producing an OLED product by an ON CELL technology and an Moalloy protection scheme can be solved, and the product quality and the production efficiency can be effectively improved.