TBC back contact solar cell and preparation method thereof
A solar cell and back contact technology, applied in the field of solar cells, can solve problems such as positioning problems and lower product yield, and achieve the effects of reducing metal recombination, reducing metal puncture, increasing current density and open circuit voltage
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Embodiment 1
[0030] Embodiment 1N-TBC back contact solar cell
[0031] Such as Figure 1-10 As shown, the N-TBC back contact solar cell in this embodiment includes an N-type silicon wafer 1, a passivation anti-reflection layer deposited on the front side of the N-type silicon wafer 1, and a first tunnel arranged on the back side of the N-type silicon wafer 1. Through oxide layer 3, p+ doped layer 4, second tunnel oxide layer 8, first silicon nitride layer 6, n+ doped layer 10, second silicon nitride layer 11, silver electrode 13 and embedded part of N-type silicon The third tunnel oxide layer 9 on the back of the chip 1.
[0032] Wherein, the resistivity of the N-type silicon wafer 1 is 0.5-15Ω·cm, and the thickness is 50-300um. All tunnel oxides are made of SiO 2 , the thickness is 1~3nm, SiO 2 The growth method is high temperature thermal oxygen method, nitric acid oxidation method, ozone oxidation method or CVD deposition method; heavily doped p+poly Si (p+ doped layer 4) and n+poly...
Embodiment 2
[0040] The preparation method of embodiment 2N-TBC back contact solar cell
[0041] This embodiment provides a kind of preparation method based on the N-TBC back contact solar cell in embodiment 1, specifically comprises the following steps:
[0042] (1), the N-type silicon wafer 1 is sequentially subjected to damage removal, texturing, cleaning, and back polishing
[0043] Select the N-type silicon substrate, remove the mechanical damage layer and oil stain with alkaline solution, and then perform conventional texturing cleaning; then perform hot alkali polishing on the back surface of the N-type silicon, such as figure 1 shown.
[0044] The N-type crystalline silicon substrate selected in this embodiment has a resistivity of 6Ω·cm and a thickness of 180um.
[0045] (2), prepare the first tunnel oxide layer 3 and the p+ doped layer 4
[0046] Such as figure 2 As shown, on the back side of the N-type crystalline silicon substrate treated in step (1), grow the first tunnel...
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