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A kind of Josephson junction satisfying large wafer size, preparation method and use

A wafer-sized, integrated technology, applied in the usage of superconductor elements, manufacturing/processing of superconductor devices, devices containing a node of different materials, etc., can solve the problem of increasing dielectric loss, dielectric loss, increasing loss, etc. problems, to achieve the effect of simple process steps, low dielectric loss, and high integration

Active Publication Date: 2022-07-12
GUSU LAB OF MATERIALS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the oblique coating method still has certain disadvantages, such as: the film thickness and resistance uniformity of the Josephson junction in the large wafer size range cannot be guaranteed, which is not conducive to high integration
At the same time, limited by the existence of the polymer material mask layer, the preparation of the Josephson junction region needs to be controlled at a low temperature range from room temperature to 200 °C, which cannot reach the optimal growth temperature of the superconducting film layer.
[0004] From the material point of view, Al has a low superconducting temperature and superconducting energy gap, which is easy to cause quasi-particle injection and increase loss
On the other hand, the chemical properties of Al are relatively active, and naturally oxidized AlO x Has a certain dielectric loss when working at low temperature
At the same time, although the oxide layer is relatively dense and can achieve a certain passivation protection for the junction area, it is still unstable in the atmospheric environment or in the photolithography process, and is prone to denaturation after being treated with moisture or chemical reagents, further increasing the dielectric strength. electrical loss and will change the critical current of the Josephson junction

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  • A kind of Josephson junction satisfying large wafer size, preparation method and use
  • A kind of Josephson junction satisfying large wafer size, preparation method and use
  • A kind of Josephson junction satisfying large wafer size, preparation method and use

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Effect test

Embodiment 1

[0072] This embodiment provides a method for preparing a Josephson junction that satisfies a large wafer size. The lower electrode Ta (110) layer and the superconducting circuit pattern are formed in steps, such as figure 1 As shown, the preparation method specifically comprises the following steps:

[0073] (I) Perform surface atomic step treatment, backside pre-coating and active oxygen-assisted surface cleaning on the substrate, deposit a Ta(110) film on the C-plane sapphire substrate, and form a superconducting circuit pattern by photolithography. Prepared by magnetron sputtering method, the growth temperature is 500°C, the working pressure is 13mTorr, the DC power is 600W, the target base distance is 110mm, and the growth thickness is 100nm;

[0074] The lower electrode Ta(110) layer is prepared by mask photolithography in the overlapping area of ​​the superconducting circuit pattern, and the lower electrode Ta(110) layer is prepared by magnetron sputtering method, includ...

Embodiment 2

[0079] The present embodiment provides a method for preparing a Josephson junction that satisfies the size of a large wafer. The lower electrode Ta (110) layer and the superconducting circuit pattern are formed in steps, and the preparation method specifically includes the following steps:

[0080](I) Perform surface atomic step treatment, backside pre-coating and active oxygen-assisted surface cleaning on the substrate, deposit a Ta(110) film on the C-plane sapphire substrate, and form a superconducting circuit pattern by photolithography. It is prepared by magnetron sputtering method, the growth temperature is 410℃, the working pressure is 5mTorr, the DC power is 400W, the target base distance is 70mm, and the growth thickness is 50nm;

[0081] The lower electrode Ta(110) layer is prepared by mask photolithography in the overlapping area of ​​the superconducting circuit pattern, and the lower electrode Ta(110) layer is prepared by magnetron sputtering method, including: first...

Embodiment 3

[0086] The present embodiment provides a method for preparing a Josephson junction that satisfies the size of a large wafer. The lower electrode Ta (110) layer and the superconducting circuit pattern are formed in steps, and the preparation method specifically includes the following steps:

[0087] (I) Perform surface atomic step treatment, backside pre-coating and active oxygen-assisted surface cleaning on the substrate, deposit a Ta(110) film on the C-plane sapphire substrate, and form a superconducting circuit pattern by photolithography. Prepared by magnetron sputtering method, the growth temperature is 600°C, the working pressure is 8mTorr, the DC power is 700W, the target base distance is 150mm, and the growth thickness is 150nm;

[0088] The lower electrode Ta(110) layer is prepared by mask photolithography in the overlapping area of ​​the superconducting circuit pattern, and the lower electrode Ta(110) layer is prepared by magnetron sputtering method, including: firstly...

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Abstract

The invention provides a Josephson junction satisfying large wafer size, a preparation method and use. ) layer, Ta(110) layer of the lower electrode is prepared on the surface of Ta 2 O 5 The oxide layer is used as an intermediate layer, and the upper electrode Ta (110) layer is formed by mask photolithography, and the Josephson junction is prepared. The present invention uses Ta(110) superconducting thin film as the lower electrode and upper electrode of the Josephson junction, and the Ta(110) film on the surface is 2 O 5 The oxide layer has the characteristics of compactness and stability. It can be passivated and optimized with piranha solution to further remove photoresist residues and ensure the stability of the superconducting circuit structure and Josephson junction. The process steps are simple, stable and controllable, and integrated. With the characteristics of high degree, it can prepare uniform and stable Josephson junctions in the large wafer size range, and is suitable for the regulation of Josephson junctions of different areas.

Description

technical field [0001] The invention belongs to the technical field of superconducting chips, and relates to a Josephson junction satisfying the size of a large wafer, a preparation method and an application thereof. Background technique [0002] As the core basic component of quantum chips, the structure of superconducting Josephson junctions and their fabrication processes have been extensively studied. How to ensure and improve the performance of the Josephson junction and simplify its fabrication process has become a research hotspot. At the same time, in order to promote the realization of general quantum computing, it is also important to prepare a stable and scalable Josephson junction that meets the large wafer size. [0003] At present, the suspension structure and double dip angle evaporation technology are still the common process methods for the preparation of Josephson junctions. A typical example is based on aluminum (Al) / alumina (AlO) x ) / Al superconducting J...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L39/24H01L39/02H01L39/12H01L39/22H10N60/01H10N60/80H10N60/85
CPCH10N60/805H10N60/855H10N60/12H10N60/0912Y02E40/60
Inventor 杨丽娜冯加贵熊康林吴艳伏李睿颖贾浩林
Owner GUSU LAB OF MATERIALS
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