Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; the channel structure is discrete on the substrate in the device region; the power supply track line is positioned in the substrate of the power supply track area; the gate structure stretches across the channel structure; the source-drain doped region is located in the channel structure on the two sides of the gate structure; the interlayer dielectric layer is located at the side part of the gate structure; the power supply rail contact plug penetrates through the partial thickness interlayer dielectric layer at the top of the power supply rail line and is in full contact with the top surface of the power supply rail line along the longitudinal power supply rail contact plug; and the source-drain contact layer is located in the interlayer dielectric layer and is in contact with the source-drain doped region, and the source-drain contact layer stretches across the power supply track line on a projection plane parallel to the substrate. The power rail contact plug is in full contact with the top face of the power rail line in the longitudinal direction, the longitudinal size of the power rail contact plug is increased, the contact area of the power rail contact plug and the power rail line is increased, and the resistance of the power rail contact plug and the contact resistance of the power rail contact plug and the power rail line are reduced.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] Logic chips are made up of standard cells. The size of the standard cell depends on the metal pitch, the height of the standard cell, the polysilicon pitch, and whether it is a single diffusion block (SDB) or a double diffusion block (DDB). Chip scaling has been driven by metal pitch (MP) and polysilicon pitch (PP) scaling for many years, but MP scaling is challenged by lithographic process limits and resistance increases, and polysilicon pitch scaling has slowed down due to device issues . The introduction of Design Process Co-Optimization (DTCO) has made compressing standard cell heights the primary scaling option. As the cell height gradually shrinks, the number of fins for a single device per cell also gradually decreases, which will also result i...

AI Technical Summary

Problems solved by technology

[0006] However, the performance of current devices still needs to be improved

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