Superconducting integrated circuit with NbN SNS Josephson junction and manufacturing method thereof
A technology of integrated circuits and manufacturing methods, which is applied in the field of superconducting electronics, can solve the problems of low operating temperature of SFQ circuits, difficulties in critical current density and maximum operating frequency of Josephson junction units, and achieve repeatability and high industrial utilization value, the effect of increasing the highest frequency
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Embodiment 1
[0065] This embodiment provides a superconducting integrated circuit with NbN SNS Josephson junction and its manufacturing method, such as figure 1 As shown, it is shown as a flow chart of the fabrication method for forming the NbN SNS Josephson junction unit, including the following steps:
[0066] S1: Provide a substrate, and form a functional material layer including a NbN bottom layer film, a metal barrier layer, and an NbN top layer film sequentially from bottom to top on the substrate;
[0067] S2: Etching the functional material layer to form a functional layer, and the functional layer includes a bottom electrode, a junction barrier layer, and a top electrode stacked upward, and is formed on the exposed surface of the functional layer and on the substrate A first isolation layer is formed on the surface;
[0068] S3: forming a first contact hole and a second contact hole penetrating through the first isolation layer, and the bottom of the first contact hole exposes th...
Embodiment 2
[0113] This embodiment provides a superconducting integrated circuit with NbN SNS Josephson junction, such as Figure 10 As shown, it is a schematic cross-sectional structure diagram of the superconducting integrated circuit with NbN SNS Josephson junction, including a substrate 1, a functional layer 2, a first isolation layer 3, a first wiring part 41, and a second wiring part 42. The second isolation layer 5, the first ground layer 511 and the second ground layer 521, wherein the functional layer 2 is located on the upper surface of the substrate 1 and includes a bottom electrode 211 stacked upward, a junction barrier layer 221 and Top electrode 231, the first isolation layer 3 covers the exposed surface of the functional layer 2 and the upper surface of the substrate 1, and the first isolation layer 3 is provided with a first contact hole 31 and a second contact hole 32, the first wiring part 41 and the second wiring part 42 respectively fill the first contact hole 31 and t...
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Abstract
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