A silicon carbide mosfet cell layout structure with integrated gated diode

Abstract

The invention relates to a cell layout structure of a silicon carbide MOSFET integrated with a gate-controlled diode, and belongs to the technical field of power semiconductor devices. The invention adopts the separation gate design, and the gated diode is integrated in a single piece; the gated diode is integrated into each MOSFET cell on the layout, and the separated gate channel of the gated diode and the MOSFET is designed to be circular on the graph, In order to solve the reliability problem caused by the electric field concentration at the edge of the separation gate. In order to obtain higher channel density, the outer channel of the MOSFET is designed to be hexagonal from the layout. Compared with the method of arranging the main and auxiliary devices separately in the traditional monolithic integration, the advantage of the present invention is that the main device MOSFET and the integrated device gate-controlled diode are uniformly arranged in the whole active area, so that both devices can obtain a larger The effective heat dissipation area improves the respective current capability and robustness.

Description

Technical field [0001] The present invention is the field of power semiconductor device technology, which involves a silicon carbide MOSFET metaphysical layout method that integrates a grille control diode. Background technique [0002] Wide -and -tape semiconductor material SIC is an ideal material for preparing high -voltage electric electronic devices. Compared to SI materials, SIC materials have high intensity of breakdown electric field (4 × 10 (4 × 10 6 V / CM), high -flowing saturation drift speed (2 × 10 7 CM / S), high thermal conductivity, good thermal stability, etc., so it is especially suitable for electronic devices for high -power, high -voltage, high temperature and anti -radiation. [0003] SIC VDMOS is a more commonly used device in SIC power devices. Compared with bipolar types, because SICVDMOS does not have a charge storage effect, it has better frequency characteristics and lower switching loss. At the same time, SIC material's wide controlband makes SIC VDMOS o...

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Problems solved by technology

[0004] However, there are two problems in the planar SiC VDMOS. One is that the density of the JFET area is relatively high, which introduces a large Miller capacitance, which increases the dynamic loss of the device; the other is that the parasitic SiC body diode conduction voltage drop is too high. , and it is a bipolar device, which has a large reverse recovery current. In addition, the bipolar degradation phenomenon caused by the silicon carbide BPD defect makes the conduction voltage drop of the body diode continue to increase with the growth of service time. Therefore, The body diode of SiC VDMOS cannot be directly used as a freewheeling diode

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