Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Semiconductor structure and forming method thereof

A semiconductor and wet etching technology, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, transistors, etc., can solve the problems of device reliability decline, semiconductor structure performance reduction, fin damage, etc., to reduce consumption and improve Fin width uniformity and height uniformity, effect of improving performance

Pending Publication Date: 2022-07-29
SEMICON MFG INT (SHANGHAI) CORP +1
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The gate oxide layer is an important structure in semiconductor devices such as MOSFETs (field effect transistors). If there are defects on the gate oxide layer, the reliability of the device will be reduced.
In the I / O area, the thickness of the gate oxide layer also has different requirements, and the gate oxide layer corresponding to the thickness requirements of different processes is easy to cause a certain degree of damage to the fin portion in the process of forming the fin portion of the I / O area. damage that degrades the performance of the semiconductor structure

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof
  • Semiconductor structure and forming method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0035] The performance of the current semiconductor structure still needs to be improved. Now combined with a method of forming a semiconductor structure to analyze the reasons why its performance still needs to be improved.

[0036] refer to Figure 1 to Figure 4 , a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure is shown.

[0037] refer to figure 1 , providing a base, including a substrate 10 and a fin portion 12 protruding from the substrate 10 , an isolation layer 11 is formed on the substrate 10 exposed by the fin portion 12 , and the isolation layer 11 covers the fin portion 12 part of the sidewall, the substrate includes a first region 10H for forming a first device and a second region 10S for forming a second device, wherein the operating voltage of the first device is greater than that of the second device Operating Voltage.

[0038] refer to figure 2 , forming a second gate oxide layer 20 conforma...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a substrate and a fin part protruding out of the substrate, the substrate comprises a first region used for forming a first device and a second region used for forming a second device, and the working voltage of the first device is greater than the working voltage of the second device; forming a first gate oxide layer covering the fin portions of the first region and the second region in a shape-preserving manner, the first gate oxide layer located in the second region being used for forming a gate dielectric layer of a second device; a second gate oxide layer covering the first gate oxide layer in a shape-preserving mode is formed, and the second gate oxide layer and the first gate oxide layer located in the first area are used for forming a gate dielectric layer of the first device; and carrying out gate dielectric layer thinning treatment, wherein the gate dielectric layer thinning treatment comprises the step of removing the second gate oxide layer in the second region. According to the scheme, the consumption of the fin parts in the second region in the process is reduced, and the width uniformity and height uniformity of the fin parts in the first region and the second region are further improved.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background technique [0002] As the integration level of semiconductor devices becomes higher and higher, the voltage and current required for the operation of semiconductor devices continue to decrease, and the switching speed of transistors is also accelerated, and the requirements for all aspects of semiconductor technology are greatly increased. A gate last process is formed, that is, a dummy gate structure is formed first, source / drain implantation and high temperature annealing processes are performed, the dummy gate structure is removed, a gate oxide layer is deposited, and finally a gate structure is formed. [0003] The gate oxide layer is an important structure in a semiconductor device such as a MOSFET (Field Effect Transistor), and if there are defects on the gate oxide ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L27/092H01L29/423H01L21/8238
CPCH01L27/0924H01L21/823821H01L21/823857H01L29/42364
Inventor 渠汇何永根黄豪俊
Owner SEMICON MFG INT (SHANGHAI) CORP
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products