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Storage structure in ferroelectric nonvolatile memory and its read method

A non-volatile memory and ferroelectric technology, applied in static memory, digital memory information, information storage, etc., can solve the problems of shorter information retention time, shorter information retention time, and higher information programming voltage

Inactive Publication Date: 2005-09-28
SEMICON TECH ACADEMIC RES CENT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, if a stacked structure of a ferroelectric film and a dielectric film is used as the gate insulating film of a field effect transistor, new problems will arise: (1) the programming voltage of information becomes high, (2) the retention time of information (data hold time) becomes shorter, etc.
However, if this structure is adopted, there will be a problem that the programming information voltage becomes high and the information retention time becomes short

Method used

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  • Storage structure in ferroelectric nonvolatile memory and its read method
  • Storage structure in ferroelectric nonvolatile memory and its read method
  • Storage structure in ferroelectric nonvolatile memory and its read method

Examples

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no. 1 example

[0050] Figure 2A with 2B It is an equivalent circuit diagram showing the memory cell structure in the ferroelectric nonvolatile memory according to the first embodiment of the present invention.

[0051] Two ferroelectric capacitors C with the same amount of remanent polarization A 、C B One side electrode of the electrode is connected to the gate electrode of the field effect transistor (MOSFET) Tr of MOS structure, and the ferroelectric capacitor C A 、C B The other electrodes are connected to terminals A and B, respectively. Transistor Tr and ferroelectric capacitor C A 、C B form a storage unit. Each ferroelectric capacitor C A 、C B The dielectric film used such as PZT (lead zirconate titanate), and the area and film thickness of the capacitor are set to the same value.

[0052] In this embodiment, the memory cell can be used as an analog memory, but in this example, to simplify its description, an example of its operation is explained where this memory cell is use...

no. 2 example

[0062] Next, a second embodiment of the present invention will be described. This embodiment is similar to the first embodiment in basic construction, but the capacitor C A The film thickness of the ferroelectric film is related to the capacitor C B The film thickness of the ferroelectric film is large enough. For example, if capacitor C B The film thickness of the ferroelectric film is set to about 0.1µm, it is better to set the capacitor C A The film thickness of the ferroelectric film is set to about 0.2-0.3 μm, that is, the capacitor C A The film thickness of the ferroelectric film is the capacitor C B 2 to 3 times the film thickness of the ferroelectric film.

[0063] The programming method of the memory in this embodiment is basically the same as that of the first embodiment, but if the gate capacitance of the MOSFET is large and the influence of the potential on the semiconductor side cannot be ignored, set the potential of the semiconductor to an electrically floa...

no. 3 example

[0072] 4A to 4C are for explaining the configuration of a ferroelectric nonvolatile memory according to a third embodiment of the present invention, wherein a perspective view of a memory cell structure is shown in FIG. 4A, Figure 4B is a graphic plan view showing the overlapped state of the gate electrode and the wiring electrode, and Figure 4C is the equivalent circuit diagram.

[0073] This embodiment is achieved by forming the structure of the first embodiment at a high density using an SOI (silicon on sapphire) substrate.

[0074]On an insulating substrate 31 composed of a silicon substrate and a silicon dioxide film formed thereon, a strip 32 of a single crystal silicon film is formed. A dielectric film 33, such as a silicon dioxide film, is formed on the above structure by deposition. The single crystal silicon thin film strip 32 consists of npn structures divided in the strip direction. In the figure, one unit portion is shown, but actually a plurality of silicon ...

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Abstract

Each of memory cells of a ferroelectric nonvolatile memory includes a MOS field effect transistor and first and second ferroelectric capacitors whose remnant polarization amounts are substantially equal to each other. One-side electrodes of the first and second ferroelectric capacitors are connected to the gate electrode of the MOS field effect transistor. Information is stored by polarizing the thin ferroelectric films of the ferroelectric capacitors. Information is read out by applying a positive voltage pulse to one of the other electrodes of the first and second ferroelectric capacitors while the other one of the other electrodes is kept in the electrically floating state. Further a negative voltage pulse having an absolute value smaller than the positive voltage pulse may be applied, if necessary.

Description

technical field [0001] The present invention relates to ferroelectric nonvolatile memories, and more particularly to devices having a ferroelectric capacitor (ferroelectric gate FET) connected to the gate of a field effect transistor of MOS (metal oxide semiconductor) or MIS (metal insulator semiconductor) structure. A ferroelectric nonvolatile memory and a readout method for reading information from the memory. Background technique [0002] If a junction is made between a semiconductor and a ferroelectric, it can be expected that a state in which holes and electrons are respectively induced on the surface of the semiconductor depends on the polarization direction of the ferroelectric. Therefore, attempts have been made to form the gate insulating film of the MOS field effect transistor using a ferroelectric to establish the above two states corresponding to "0" and "1" and to form a non-volatile memory whose contents are not erased even when the power is turned off. Volati...

Claims

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Application Information

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IPC IPC(8): G11C14/00G11C11/22H01L21/8246H01L21/8247H01L27/10H01L27/105H01L27/115H01L29/788H01L29/792
CPCH01L27/11502G11C11/223H10B53/00G11C11/22
Inventor 石原宏
Owner SEMICON TECH ACADEMIC RES CENT
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