N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same

Abstract

An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration N-type implantation, and an N-driver coupled to the boost gate stack.

Description

[0001] 1. Field of the Invention[0002] The present invention generally relates to an NMOS driver circuit, and a method of fabricating an NMOS driver circuit with improved performance and reliability.[0003] 2. Description of the Related Art[0004] An N-channel metal oxide semiconductor (NMOS) driver is known to have certain advantages as compared to conventional complementary oxide semiconductor (CMOS) drivers (e.g., such as P-channel field effect transistors (PFETs), N-channel field effect transistors (NFETS) and the like), such as smaller area, a switching performance gain, and less gate oxide stress.[0005] The NMOS driver has a smaller area compared to a CMOS driver based on similar performance. Such a smaller area results from the CMOS device (e.g., PFETs, NFETs, etc.) having a design width which is double that of the NFET device because of a difference in hole and electron mobility. The mobility of electrons, which are the conducting carriers for NFETs, is about two times that of...

AI Technical Summary

Benefits of technology

[0028] With the unique and unobvious features of the invention, the junction breakdown problem found in conventional NMOS drivers is overcome. Further, an NMOS driver is produced which has a smaller area, with similar or better performance to that of the conventional NMOS drivers, with improved reliability. Such improved reliability is made possible in part by increasing junction breakdown voltage of the boost node of the NMOS driver from 7V to more than 10V.

[0029] Moreover, less gate oxide stress results with the structure and method of the present invention. The inventive structure can be advantageously provided (and indeed is more suitable) for negative WL low application.

Problems solved by technology

Since a dual-workfunction-gate process requires extra mask steps and extra implant steps, it is generally more expensive than a single-work function-gate process.

However, when the single-work function-gate process is used (e.g., N+ polysilicon gate only), the PFETs typically are buried channel PFETs, which have a substantially worse short-channel effect as compared with surface channel PFETs, or NFETs.

When the threshold voltage is below the designed target, excessive leakage current may occur even when the gate should supposedly be "OFF".

Buried channel PFETs also tend to be more susceptible to the "punchthrough effect".

When punchthrough occurs, the drain current will no longer be controlled by the gate voltage.

The loss of gate control can lead to circuit malfunction.

This not only leads to circuit area penalty, but also to performance degradation.

One of the limitations for the highest boosted WL voltage Vpp is the reliability of the buried channel PFET used in the WL driver region.

Carriers with high enough energy can overcome the barrier at the gate oxide interface, travel towards the gate oxide, and cause permanent damage to the gate oxide interface.

However, the NMOS driver devices also have some drawbacks.

("A 20 Ns, 64M DRAM with Hierarchical Array Architecture", IEEE J. of SSC, Vol. 32, No. 9, September 1996, p.1302), serious reliability problems develop related to junction breakdown on a boosted node, especially during a burn-in condition when a much higher voltage is applied (e.g., typically 1.5.times.that of the nominal operating voltage).

As a result, damage may occur to the junction.

That is, the reverse bias voltage may lead to junction breakdown and high leakage current between the junction and the substrate.

In the conventional NMOS driver, this condition can result in permanent damage to the boost device, or at a minimum high junction leakage.

The consequence of such damage or leakage is that the boosted node voltage of the NMOS driver can no longer be sustained during wordline operation.

This limitation is a main reason why an NMOS driver is not utilized in today's high performance and high density memory design.

Images