Semiconductor device having a thin film capacitor and method for fabricating the same

Abstract

In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO₂, HfO₂, (Zr_x, Hf_1-x)O₂ (0<x<1), (Zr_y, Ti_1-y)O₂ (0<y<1), (Hf_z, Ti_1-z)O₂ (O<z<l), (Zr_k, Ti_l, Hf_m)O₂ (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.

Description

BACKGROUND OF THE INVENTION [0001] The present invention relates to a semiconductor device having a thin film capacitor and a method for fabricating the same. [0002] Heretofore, in a general purpose DRAM, Ta2O5 having a high dielectric constant has been considered as a capacitor dielectric film in a memory cell. In this case, it is an ordinary practice that a lower electrode of a capacitor is formed of a polysilicon layer which can be formed to have a concavo-convex surface (for example, so called HSG (hemi-spherical grain) structure) in order to increase a capacitance per a unitary area. In order to form this polysilicon layer, a high temperature process on the order of 700 to 900 degrees Celsius is required. [0003] On the other hand, in a logic mixed DRAM in which a logic section and a memory section are formed on the same chip, gate electrodes and source / drain diffused regions in the logic section are required to be provided with a cobalt (Co) silicide for a speedup of transistor...

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Benefits of technology

[0022] Another object of the present invention is to provide a capacitor which can realize a large capacitance and a small leakage current as a capacitor for a DRAM cell in a memory section of a semiconductor device having the memory section...

Problems solved by technology

Therefore, in a process after formation of the cobalt silicide layer, the process temperature cannot be elevated.

Accordingly, if Ta2O5 is used to form a capacitor dielectric film in the memory section of the logic mixed DRAM and if a polysilicon layer is used to form a lower capacitor electrode, a high temperature process is required to form the polysilicon layer, with the result that the transistors in the logic section become deteriorated through the high temperature process.

Therefore, in the generation of the gate length of 0.15 micron and in succeeding generations, it is not possible to use the polysilicon for the lower capacitor electrode.

However, a resonance frequency of the laminated ceramic capacitor is on the order of about 80 MHz, and therefore, when the LSI is speeded up to several hundred MHz to several GHz, a satisfactory electric charge compensation cannot be carried out, so that it does not function as the decoupling capacitor.

As a result, even if the thickness of the Ta2O5 film is reduced, a large capacitance cannot be obtained.

In addition, because of the oxidation occurring in the post anneal, a concavo-convex or a pe...

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