Fabrication method of semiconductor integrated circuit device

Abstract

To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] The present application claims priority from Japanese patent application No. 2003-372323, filed on Oct. 31, 2003, the content of which is hereby incorporated by reference into this application. BACKGROUND OF THE INVENTION [0002] The present invention relates in general to technology for the manufacture of a semiconductor integrated circuit device, and, more particularly, to a technique that is effective when applied to electrical testing of a semiconductor integrated circuit device having a plurality of electrode pads disposed at narrow pitches. [0003] For example, in the burn-in test of a semiconductor device having a protruding electrode, using a semiconductor device testing apparatus having a plurality of pyramid-shaped contact terminals protruding toward the semiconductor device, at least one contact terminal is brought into contact, at the ridge line or slope thereof, with one of the protruding electrodes, thereby bringing the semic...

AI Technical Summary

Benefits of technology

[0008] In recent years, semiconductor integrated circuit devices have been discussed to perform many functions and a plurality of circuits tend to be integrated in one semiconductor chip (which will hereinafter simply be called a “chip”). In addition, a reduction in the manufacturing cost of semiconductor integrated circuit devices can be promoted by increasing the number of chips available from one wafer by miniaturizing the semiconductor elements and interconnects, while narrowing the area of the chip. In order to attain this, not only is the number of test pads (bonding pads) increased, but also these test pads are disposed at narrower pitches and the areas of the test pads are narrowed. With narrowing of the pitch of the test pads, it becomes difficult to locate probes so that they come into contact with the test pads when a prober having cantilever type probes is used for the probe testing.

[0010] In addition, wiping of the probe on the surface of the test pad shaves off a portion of the test pad, and shavings thus generated adhere to the tip portion of the probe. The shavings adhere to the tip portion of the probe one after another by the repetition of probing, which finally disturbs the electrical connection between the probe and the test pad. After probing is conducted a predetermined number of times, the probe should be cleaned by rubbing the tip portion of the probe with a certain cleaning sheet. The inevitable addition of this cleaning step prolongs the probe testing step, which also prolongs the fabrication time of the semiconductor integrated circuit device, resulting in a rise in the production cost of the semiconductor integrated circuit device.

[0013] At present, a method of reducing the number of test pads to be brought into contact with probes has been investigated utilizing DFT (Design For Testability) or BIST (Built In Self Test). Use of DFT (Design for Testability) or BIST (Built In Self Test) however needs disposal of new test pads. For the purpose of preventing elements or interconnects from being damaged by the impact upon contact of the probe with the test pad, the test pad is disposed in an input / output region having neither elements nor interconnects formed therebelow. With an increase in the operation speed of a semiconductor integrated circuit device, on the other hand, there is a growing need for disposal of a large number of power supply pads in their input / output regions in order to reduce noise (to reduce source impedance). In a chip of limited size, the size of each input / output region is also limited. The disposal of the power supply pads therefore makes it difficult to keep a region for the disposal of the above-described test pad that is used for DFT or BIST.

[0015] Another object of the invention is to provide, upon testing of a semiconductor integrated circuit device, a technique that is capable of reducing damage to the test pads.

[0016] A further object of the invention is to provide a technique that is capable of shortening the electrical testing step in the fabrication of a semiconductor integrated circuit device.

[0178] The present invention makes it possible to carry out electrical testing (probe testing) of a semiconductor integrated circuit device having test pads disposed at narrow pitches.

Problems solved by technology

With narrowing of the pitch of the test pads, it becomes difficult to locate probes so that they come into contact with the test pads when a prober having cantilever type probes is used for the probe testing.

Wiping of the probes will not only break the natural oxide film formed over the surface of each test pad, but also forms a dent on the surface of the test pad.

This leads to a problem in that the adhesive force of a bonding wire connected to the test pad in the later step is inevitably lowered.

There is also a fear that, as the area of the test pad decreases, the tip portion of the probe deviates from the test pad and a short-circuit occurs between the two test pads.

The shavings adhere to the tip portion of the probe one after another by the repetition of probing, which finally disturbs the electrical connection between the probe and the test pad.

The inevitable addition of this cleaning step prolongs the probe testing step, which also prolongs the fabrication time of the semiconductor integrated circuit device, resulting in a rise in the production cost of the semiconductor integrated circuit device.

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