Multiprocessor computer system

Abstract

The present invention relates to the architecture and use of a computer processor optimized for instruction and data processing. The computer processor includes a main processor element in operative communication with a main memory for storing data, and sub-processor elements in operative communication with the main processor element for processing the data. Each of the sub-processor elements including a dedicated local memory for storing instructions and data. The main processor desirably comprises a primary processor core, and the sub-processor elements desirably include a set of coprocessors. One of the coprocessors may be an embedded coprocessor that performs error checking in the primary processor core. Another one of the coprocessors may be a vector processing unit. A program can directly control the vector processing unit or may indirectly control it via the primary processor core.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of application Ser. No. 10 / 694,482, filed on Oct. 27, 2003, which is a continuation of application Ser. No. 09 / 502,671, filed on Feb. 11, 2000 which issued as U.S. Pat. No. 6,807,620, on Oct. 19, 2004, the disclosures of which are hereby incorporated by reference in their entirety.FIELD OF THE INVENTION [0002] The present invention relates to computer system architectures. More particularly, the present invention relates to the architecture and use of a computer system optimized for efficient modeling of graphics. BACKGROUND OF THE INVENTION [0003] High resolution, real time computer graphics are an important aspect of computer systems, particularly simulators (such as flight simulators) and game machines. Computer games, in particular, involve a great deal of computer graphics. Computer systems used as game machines, therefore, must handle far more computer graphics than a standard business computer u...

AI Technical Summary

Benefits of technology

The present invention provides an improved computer system for simulators and game machines. The system includes a new computer architecture with a main processor and two co-processors, a frame buffer and rendering system on the same integrated chip. The main processor contains two co-processors for geometry modeling and a central processing unit (CPU) for complex irregular geometry processing. The system also includes a multimedia instruction set using 128-bit registers in parallel, a scratchpad RAM for fast data transfer, and a common protocol data jack for multiple types of inputs and outputs. The sub-processor elements operate as independent processors based on instructions stored in dedicated local memory. The system provides faster and more efficient processing for high-resolution texture data and enables sophisticated behavioral and physical modeling in real-time.

Problems solved by technology

The game developer is faced with many limitations.

Prior art game machines, however, make the implementation of such graphics difficult.

High resolution graphics are computationally expensive and difficult to render in the time required by a fast moving game.

Current graphics co-processors, if implemented at all in game consoles, have difficulty supplying the bandwidth necessary to render high resolution, real time graphics.

Prior art game machines also do not permit easy behavioral and physical modeling of game objects.

However, such modeling is computationally expensive, requiring many floating point operations, and the standard CPU is not optimized for such calculations.

Prior art game machines also cannot easily deal with compressed video data.

As game developers code larger and larger game worlds, they are in danger of running out of space in removable media.

The use of compression techniques to store various kinds of data, such as graphics data, is limited by the need to decompress such data quickly for use in a real time, interactive game.

Prior art game machines also are generally restricted to gaming applications.

However, limitations in input and output interfaces render such applications difficult.

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