Temperature monitoring in a semiconductor device by using an pn junction based on silicon/germanium material

Abstract

By incorporating germanium material into thermal sensing diode structures, the sensitivity thereof may be significantly increased. In some illustrative embodiments, the process for incorporating the germanium material may be performed with high compatibility with a process flow for incorporating a silicon / germanium material into P-channel transistors of sophisticated semiconductor devices. Hence, temperature control efficiency may be increased with reduced die area consumption.

Description

BACKGROUND[0001]1. Field of the Disclosure[0002]Generally, the present disclosure relates to the formation of integrated circuits, and, more particularly, to thermal sensing techniques in semiconductor devices on the basis of diode structures.[0003]2. Description of the Related Art[0004]The fabrication of integrated circuits requires a large number of circuit elements, such as transistors and the like, to be formed on a given chip area according to a specified circuit layout. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips, ASICs (application specific ICs) and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and / or power consumption and / or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and...

AI Technical Summary

Benefits of technology

[0012]Generally, the subject matter disclosed herein relates to semiconductor devices and methods providing enhanced temperature sensing capabilities in semiconductor devices while reducing area consumption and / or providing higher efficiency for evaluating temperatures, for instance, of critical device regions, by enhancing the temperature sensitivity of thermal sensing diode structures. For this purpose, the present disclosure contemplates the usage of a semiconductor material having a reduced band gap energy compared to silicon, which therefore may result in an increased temperature sensitivity of a diode structure having a PN junction including the material of reduced band gap energy. In illustrative aspects disclosed herein, a germanium material may be incorporated into the diode structure for silicon-based semiconductor devices, thereby providing the enhanced temperature sensitivity which may therefore result in less area consumption of diode structures used for thermal sensing applications compared to conventional silicon diode structures. In some illustrative aspects disclosed herein, the incorporation of germanium material, for instance in the form of a silicon / germanium alloy material, may be accomplished with a high degree of compatibility with process techniques used for forming transistor elements in the device layer of SOI devices or bulk devices and also within the crystalline silicon substrate of SOI devices when germanium material may be used for performance enhancement of transistor elements, such as P-channel transistors, as may typically be the case for sophisticated semiconductor devices. Consequently, temperature sensitivity of the thermal sensing diode structures may be enhanced, thereby resulting in reduced area consumption, while substantially avoiding additional process complexity when using germanium material for providing strain-inducing mechanisms in at least one type of transistor element. Thus, an increased degree of coverage of areas of interest within a die region may be accomplished, since the thermal sensing diodes of reduced size may provide enhanced flexibility with respect to design constraints for critical device areas, as previously explained. For this reason, overall die-internal temperature control may be enhanced, thereby increasing the overall reliability of advanced semiconductor devices.

Problems solved by technology

Furthermore, the reduced feature sizes may also be accompanied by reduced switching speeds of the individual transistors, thereby contributing to increased power consumption in MOS circuits, since the reduced switching speeds allow the operation of the transistors at higher switching frequencies, which in turn increases the power consumption of the entire device.

In sophisticated applications using densely packed integrated circuits, the heat generation may reach extremely high values due to the dynamic losses caused by the high operating frequency, in combination with a significant static power consumption of highly scaled transistor devices, owing to increased leakage currents that may stem from extremely thin gate dielectrics, short channel effects and the like.

Since external heat management systems may not enable a reliable estimation of the die-internal temperature distribution due to the delayed thermal response of the package of the semiconductor device and the possibly insufficient spatial temperature resolution, these external concepts may have to be designed so as to take into consideration these restrictions and provide sufficient operational margins with respect to heat control, or to risk otherwise overheating and thus possibly destruction of specific critical circuit portions.

The incorporation of a plurality of temperature-sensitive circuits, however, may result in a significant “consumption” of valuable real estate of the semiconductor die, which may typically cause a “competitive” situation during circuit design between actual circuit portions and temperature-sensitive areas.

Therefore, frequently, the temperature-sensitive circuit portions are treated with reduced priority compared to the “actual” circuit portions, which may finally result in a circuit design in which the temperature-sensitive circuits are positioned in less than ideal temperature sensing locations.

For instance, the design of performance-critical circuit portions of the device that may be operated at higher speed or frequencies may not be compatible with the provision of sensor elements in these critical areas, for example, due to undesired lengthening of the signal routing and reduction of speed.

Hence, although these performance-critical areas usually generate a significantly higher amount of heat, the temperature of such “hot spots” may not be reliably measured, since the temperature-sensitive circuits are positioned by the design constraints at distant locations.

Therefore, in this case, damage of the performance-critical areas may occur or respective heat management strategies may be required to take into account the discrepancy of the measurement data and the actual thermal conditions in the performance-critical areas.

Similarly, the thermal response of the temperature-sensitive circuits may be affected by the shielding effect of materials and structures that may be provided in the vicinity of the temperature-sensitive circuits.

For example, due to the reduced heat dissipation capability of semiconductor-on-insulator (SOI) devices caused by the buried insulating layer, on which the actual “active” device layer is formed, the corresponding sensing of the momentary temperature in SOI devices is of particular importance, wherein, additionally, the design-dependent positioning of the temperature sensitive circuits may further contribute to a less efficient overall temperature management in sophisticated SOI devices.

Thus, in addition to the shielding effect of the buried insulating layer, at least some additional process steps may be required, for instance, for etching through the semiconductor layer or a corresponding trench isolation area and through the buried insulating layer in order to expose the crystalline substrate material, thereby contributing to the overall process complexity.

Furthermore, the temperature-sensing diodes, in combination with an appropriate evaluation circuit, may also be subject to similar design constraints as described above, irrespective of whether a bulk architecture or an SOI architecture is considered.

Hence, currently employed die-internal temperature monitoring mechanisms, although providing significant advantages over external temperature management systems, may suffer from increased die area consumption due to low temperature sensitivity, possibly in combination with reduced proximity to hot spots, which may result in reduced reliability of the die-internal temperature control.

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