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Lowering tungsten resistivity by replacing titanium nitride with titanium silicon nitride

a technology of titanium silicon nitride and tungsten resistivity, which is applied in the direction of electrical equipment, basic electric elements, and semiconductor devices. it can solve the problems of increasing processing time, tungsten film and electrode stack resistivity may jump very high, and the resistivity of tungsten film and the stack may be low

Inactive Publication Date: 2014-01-02
APPLIED MATERIALS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This patent relates to methods and apparatus for making integrated circuits. It describes a process for forming a gate electrode and associated layers. One embodiment involves a semiconductor device with a conductive film layer, a refractory metal silicon nitride film layer, and a tungsten film layer. Another embodiment involves a method of depositing a tungsten thin film by using a plasma in a processing region with a titanium silicon alloy target. The technical effects of this patent are improved methods for making integrated circuits and the deposition of high-quality tungsten in a cost-effective manner.

Problems solved by technology

Additionally, tungsten is a highly refractive material which offers good oxidation resistance and also lower resistivity.
Additionally, when thin film tungsten is combined with other materials such as WN or TiN, the resistivity of the tungsten film and the electrode stack may jump very high.
Although this solution provides decreased resistivity, it requires the use of an additional chamber to deposit the silicon containing interlayer which increases processing time and correspondingly increases cost of ownership.
In the ambient environment, the substrates are exposed to mechanical and chemical contaminants, such as particles, moisture, and the like, that may damage the gate structures being fabricated and possibly form an undesired interfacial layer, e.g., native oxide, between each layer while transferring.
As gate structures become smaller and / or thinner to increase the device speed, the detrimental effect of forming interfacial layers or contamination becomes an increased concern.
Additionally, the time spent on transferring the substrate between the cluster tools decreases productivity in manufacture of the field effect transistors.

Method used

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  • Lowering tungsten resistivity by replacing titanium nitride with titanium silicon nitride
  • Lowering tungsten resistivity by replacing titanium nitride with titanium silicon nitride
  • Lowering tungsten resistivity by replacing titanium nitride with titanium silicon nitride

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Embodiment Construction

[0026]Embodiments of the invention generally provide a gate electrode stack structure having a reduced sheet resistance (Rs) or resistivity and methods and apparatuses of forming the same. In one embodiment, the gate electrode stack structure may be formed for a memory type semiconductor device, such as a DRAM type integrated circuit.

[0027]Physical Vapor Deposition (PVD) of tungsten (W) is the material choice for DRAM gate electrodes. Gate electrode stacks typically comprise layers of Ti / WN / W, TiN / WSi / WN / W, TiN / WN / W, TiN / WSi / WN / W or combinations thereof depending on the desired integration scheme. The TiN layer acts as a diffusion barrier preventing interaction between the Poly-Si layer and W layers during subsequent RTP anneal steps. W resistivity on SiO2 is about 9.0 uohm-cm for a 500 Å film. W resistivity on TiN is about 24 uohm-cm but the resistivity can be lowered to 11 uohm-cm by inserting a thin silicon layer (2 environment. In certain embodiments, TiSiN may be deposited usin...

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Abstract

Semiconductor devices, methods and apparatus for forming the same are provided. The semiconductor device includes a substrate having a source and drain region and a gate electrode stack on the substrate between the source and drain regions. The gate electrode stack includes a conductive film layer on a gate dielectric layer, a refractory metal silicon nitride film layer on the conductive film layer, and a tungsten film layer on the refractory metal silicon nitride film layer. In one embodiment, the method includes positioning a substrate within a processing chamber, wherein the substrate includes a source and drain region, a gate dielectric layer between the source and drain regions, and a conductive film layer on the gate dielectric layer. The method also includes depositing a refractory metal silicon nitride film layer on the conductive film layer and depositing a tungsten film layer on the refractory metal silicon nitride film layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application claims benefit of U.S. provisional patent application Ser. No. 61 / 665,159, filed Jun. 27, 2012, which is herein incorporated by reference.BACKGROUND[0002]1. Field[0003]Embodiments of the present invention generally relate to methods and an apparatus of forming integrated circuits. More particularly, embodiments of the invention relate to methods and an apparatus for forming a gate electrode and associated layers.[0004]2. Description of the Related Art[0005]Integrated circuits may include more than one million micro-electronic devices such as transistors, capacitors, and resistors. One type of integrated circuit is field effect transistors (e.g., metal-oxide-semiconductor field effect transistors (MOSFET or MOS)) that are formed on a substrate (e.g., a semiconductor substrate) and cooperate to perform various functions within the circuit. A MOSFET transistor comprises a gate structure disposed between source and drain regi...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/768H01L29/66H01L29/78
CPCH01L21/76889H01L29/78H01L29/66477H01L21/28061H01L29/4941H01L21/2855H01L29/40114H10B12/05H01L21/285H01L21/28568
Inventor GANDIKOTA, SRINIVASLIU, ZHENDONGLEI, JIANXINJAKKARAJU, RAJKUMAR
Owner APPLIED MATERIALS INC
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