Integrated circuit apparatus

Abstract

An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to an integrated circuit apparatus having an SRAM cell array formed of CMOSFET and, particularly, to an integrated circuit apparatus capable of reducing the effects of latch-up that occurs in an SRAM cell array.[0003]2. Description of Related Art[0004]An integrated circuit having a complementary metal oxide semiconductor field effect transistor (CMOSFET) is susceptible to latch-up that an abnormal current flows between a power supply and a ground of the integrated circuit, caused by a parasitic bipolar transistor with a thyristor structure in CMOSFET turning ON upon application of an overvoltage to an input / output terminal or the like.[0005]The reduction in a power supply voltage with miniaturization of an integrated circuit and the implementation of shallow trench isolation (STI) for device isolation have contributed to the improvement in latch-up resistance. At the same time, since a PN i...

AI Technical Summary

Benefits of technology

[0017]According to another aspect of the present invention, there is provided an integrated circuit apparatus that includes a static random access memory (SRAM) cell array including a plurality of memory cells formed of complementary field effect transistors arranged lattice-like, a power line placed in each 1-bit sequence of the SRAM cell array, a detector detecting occurrence of an effect of a parasitic bipolar transistor or a snap-back effect that is similar thereto for each 1-bit sequence and outputting a detection signal, and a power controller controlling a voltage to be supplied to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line placed in a 1-bit sequence where the occurrence of an effect of a parasitic bipolar transistor or a snap-back effect that is similar thereto is detected by the detector down to a predetermined value according to the detection signal.

[0019]The integrated circuit apparatus of the present invention having the above configuration can limit the range that is affected by the effect of a parasitic bipolar element such as latch-up or a snap-back effect similar thereto to the range of a 1-bit sequence of the SRAM cell array. Further, since it is possible to limit the range where data is lost due to the effect of a parasitic bipolar element such as latch-up or a snap-back effect similar thereto, it facilitates the recovery of lost data by ECC processing.

[0021]This configuration allows recovering the data lost by the effect of a parasitic bipolar device such as latch-back or a snap-back effect similar thereto by ECC processing. It is therefore possible to avoid the affect of data loss due to latch-up or other effects of a parasitic bipolar device or a snap-back effect in an integrated circuit apparatus having an SRAM cell array formed of CMOSFET.

[0022]The present invention can reduce the effects of data loss due to latch-up or other effects of a parasitic bipolar device or a snap-back effect of MOSFET that is similar thereto in an integrated circuit apparatus having an SRAM cell array formed of CMOSFET.

Problems solved by technology

An integrated circuit having a complementary metal oxide semiconductor field effect transistor (CMOSFET) is susceptible to latch-up that an abnormal current flows between a power supply and a ground of the integrated circuit, caused by a parasitic bipolar transistor with a thyristor structure in CMOSFET turning ON upon application of an overvoltage to an input / output terminal or the like.

At the same time, since a PN isolation interval decreases due to the miniaturization of an integrated circuit, the ability of a parasitic bipolar transistor that causes latch-up increases and therefore the problem of latch-up still remains.

Further, since a gate length of MOSFET also decreases like in the parasitic bipolar, snap-back behavior is also likely to occur at a low voltage.

The problem of latch-up is particularly serious in an SRAM cell array that is composed of CMOS memory cells with a low density of a well potential contact and a substrate potential contact.

Occurrence of latch-up in the SRAM cell array leads to not only breakdown of the data stored in the memory cell but also hard errors if the latch-up is left unsolved.

Thus, even if hard errors are avoided by placing a detector between the power line and ground line to detect latch-up and blocking power supply, data of the entire memory cells affected by latch-up can be lost.

If latch-up occurs in such a cell array, the data retained in the entire memory cells of the 8-bit sequence supplied with power through the pair of power supply line and ground line is lost.

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