Method of making nonvolatile semiconductor memory

Abstract

The nonvolatile semiconductor memory of this invention includes: a semiconductor substrate; a plurality of memory cells formed in a matrix on the semiconductor substrate, each of the memory cells including a first insulating film formed on the semiconductor substrate, a floating gate formed on the first insulating film, and a control gate formed on the floating gate via a second insulating film sandwiched therebetween, a source diffusion region, and a drain diffusion region; a diffusion layer formed in a portion of the semiconductor substrate located between two of the memory cells adjacent in a first direction, the diffusion layer including the drain diffusion region for one of the two memory cells and the source diffusion region for the other memory cell; a word line formed by connecting the control gates of the memory cells lined in the first direction; and a bit line formed by connecting the diffusion layers lined in a second direction substantially perpendicular to the first direction, wherein the memory cells have a structure in which a tunnel current flows between the drain diffusion region and the floating gate of one of the two adjacent memory cells via the first insulating film when a predetermined voltage is applied to the diffusion layers and no tunnel current flows between the diffusion layer and the floating gate of the other memory cell.

Description

BACKGROUND OF THE INVENTION1. Field of the Invention:The present invention relates to a nonvolatile semiconductor memory using a Fowler-Nordheim (FN) tunnel current for writing and erasing, and a driving method and fabrication method for such a nonvolatile semiconductor memory. More specifically, the present invention relates to a flash memory, and a driving method and fabrication method for the flash memory.2. Description of the Related Art:Conventional general flash memories are classified into the type using hot electron injection for writing and the type using an FN tunnel current for writing.FIG. 47 is a sectional view of memory cells of a conventional flash memory 500 of the type using hot electron injection. FIG. 48 is an equivalent circuit of a memory cell array of the flash memory 500.Referring to FIG. 47, the flash memory 500 includes a semiconductor substrate 151, a tunnel insulating film 153 formed on the semiconductor substrate 151, and floating gates 155 formed on the ...

AI Technical Summary

Benefits of technology

Thus, according to the present invention, an asymmetric memory cell where the coupling capacitance of the floating gate is asymmetric between the source diffusion region side and the drain diffusion region side at writing is used. Accordingly, when voltages are applied to a word line and bit lines (drain diffusion layers) connected with a selected memory cell (selected cell), no data is written in a non-selected cell of which the source diffusion region is connected with the selected bit line. Such an asymmetric memory cell can be realized by having the impurity density of the drain diffusion layer higher than that of the source diffusion layer. Since the floating gate is capacitively coupled with the high-density drain diffusion layer, a tunnel current easily flows between the floating gate and the drain diffusion layer via the tunnel insulating film. In contrast, the impurity density of the source diffusion layer capacitively coupled with the floating gate is low even if the same voltage as that applied to the drain diffusion layer is applied to the source diffusion layer. The surface of this low-density source diffusion layer is thus depleted, lowering the electric field applied to the tunnel insulating film and thus preventing the tunnel phenomenon from occurring. Thus, in the non-selected cell sharing the bit line with the selected cell, no tunnel current flows since the floating gate thereof is capacitively coupled with the low-density source diffusion layer of the shared bit-line, preventing data from being mistakenly written in the non-selected cell.

The above asymmetric memory cell can also be realized by forming a tunnel insulating film only between the drain diffusion layer and the floating gate. In such a case, when voltages are applied to a word line and bit lines of a selected cell, since the floating gate of the selected cell is coupled with one of the bit lines via a tunnel insulating film with a smaller thickness, tunnel current flows easily. As for the non-selected cell which is connected with the same word line and shares the same bit line, the floating gate is capacitively coupled with the bit line via the gate insulating film with a comparatively large thickness. Thus, no tunnel current is allowed to flow through the thick gate insulating film. Accordingly, it is possible to employ the virtual ground method where one bit line is shared by two adjacent memory cells without writing data mistakenly in a non-selected cell in the write operation using a tunnel current.

Thus, the invention described herein makes possible the advantages of (1) providing a nonvolatile semiconductor memory using an FN tunnel current for writing and erasing and employing the virtual ground method for driving a memory cell array thereof, (2) providing a driving method of such a nonvolatile semiconductor memory, (3) providing a fabrication method of such a nonvolatile semiconductor memory, (4) providing a nonvolatile semiconductor memory with high write efficiency and reliability where a current flowing into a semiconductor substrate at writing is reduced, (5) providing a driving method of such a nonvolatile semiconductor memory, and (6) providing a fabrication method of such a nonvolatile semiconductor memory.

Problems solved by technology

The efficiency of electron injection (write efficiency) is generally poor.

Since the write current is large (about 1 mA), power consumption at writing is large.

Thus, the conventional flash memory of the type using an FN tunnel current for writing cannot employ the virtual ground method.

This makes it difficult to increase the capacitance coupling ratio of the control gate.

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