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Process for producing semiconductor device

a semiconductor and process technology, applied in the direction of semiconductor devices, basic electric elements, electrical equipment, etc., can solve the problems of complex process, increased number of steps in the process, damage to film having a low dielectric constant, etc., and achieve the effect of reducing wiring capacitance, reducing wiring capacitance, and generally remarkably increasing wiring capacitan

Inactive Publication Date: 2009-06-16
SONY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach effectively reduces wiring capacitance, enhances mechanical strength, and minimizes defects by using xerogel or fluorine resin films between wirings and organic films elsewhere, enabling precise pattern formation and simplified resist processing even with misalignment.

Problems solved by technology

However, as the organic polymer is an expensive material, taking the balance between increase in cost and improvement in performance of the semiconductor device into consideration, it has been studied a structure, in which only the inter level dielectric having groove wiring formed therein is formed with the organic polymer, and the inter level dielectric having a via hole formed therein is formed with silicon oxide or silicon oxide fluoride, which has been conventionally used.
The scale down of the wiring width and reduction of the interval bring about not only the aspect ratio of the wiring itself, but also the aspect ratio of the space among the wiring, and as a result, and thus difficulties are caused in the techniques for forming narrow and long wiring and the technique for filling a gap among fine wiring with an inter level dielectric.
Thus, the process becomes complicated, and simultaneously the number of steps contained in the process is increased.
However since a resist comprising an organic film is used in the patterning technique used in the conventional process for producing a semiconductor device, there is a problem in that the film having a low dielectric constant is damaged in the step of removing the resist.
The application of xerogel to a semiconductor device is difficult at present due to a demand of various kinds of reliability.
That is, xerogel contains from 50 to 90% of pores by volume and thus has a problem in mechanical strength.
As a result, the shoulder parts of the bottom of the wiring groove and the mask layer are cut by a sputtering phenomenon, and a wiring groove and a via hole having a good shape are difficult to be obtained.
In the process technique shown in FIGS. 1A to 1F, when the wiring groove is formed beyond. the via hole due to misalignment, the contact area of the via hole becomes small to cause problems, such as increase of the contact resistance, defective filling of the metal in the via hole, and deterioration of resistance to electro-migration.

Method used

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  • Process for producing semiconductor device
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Examples

Experimental program
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first embodiment

[0043]the process for producing a semiconductor device according to the invention will be described below with reference to the process diagram shown in FIGS. 3A to 3F, 4G and 4H.

[0044]As shown in FIG. 3A, an underlying substrate 11 comprises, for example, a substrate 51 having thereon transistors (not shown in the figure), and an inter metal dielectric 52 covering thereon, in which wiring 53 is formed. A first film having a low dielectric constant 13 to be a lower layer of an inter level dielectric 12 is formed on the underlying substrate 11 to a thickness of, for example, from 300 to 800 nm. The first film having a low dielectric constant 13 becomes an inter level dielectric (ILD) between wiring layers, and can be formed with an organic film having a specific inductive capacity of about 2.5. In this embodiment, an organic polymer totally called as polyaryl ether is employed. Specific examples of the polyaryl ether include flare (a tradename, produced by Aliedsignal Inc.), SILK (a ...

second embodiment

[0078]the process for producing a semiconductor device according to the invention will be described below with reference to the process diagram shown in FIGS. 5A to 5C. In FIGS. 5A to 5C, the same symbols are attached to the same constitutional components as in FIGS. 3A to 3F, 4G and 4H.

[0079]As shown in FIG. 5A, an underlying substrate 11 comprises, for example, a substrate 51 having thereon transistors (not shown in the figure), and an inter metal dielectric 52 covering thereon, in which wiring 53 is formed. A first film having a low dielectric constant 13 to be a lower layer of an inter level dielectric 12 on the underlying substrate 11 is formed, for example, with an inorganic film having a thickness of from 300 to 800 nm.

[0080]A second film having a low dielectric constant 14 to be an upper layer of the inter level dielectric 12 is formed to a thickness, for example, of 400 nm on the first film having a low dielectric constant 13. The second film having a low dielectric constan...

third embodiment

[0093]the process for producing a semiconductor device according to the invention will be described below with reference to the process diagram shown in FIGS. 6A to 6F. In FIGS. 6A to 6F, the same symbols are attached to the same constitutional components as in FIGS. 3A to 3F.

[0094]As shown in FIG. 6A, an underlying substrater 11 comprises, for example, a substrate 51 having thereon transistors (not shown in the figure), and an inter metal dielectric 52 covering thereon, in which wiring 53 is formed. A first film having a low dielectric constant 13 to be a lower layer of an inter level dielectric 12 is formed to a thickness of, for example, from 300 to 800 nm on the underlying substrate 11. The first film having a low dielectric constant 13 becomes an inter level dielectric (ILD) between wiring layers, and can be formed with an organic film having a specific inductive capacity of about 2.5. For example, it can be formed with the same material as described for the first embodiment in...

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Abstract

A process for producing a semiconductor device for forming a highly reliable wiring structure is provided that solves the problem occurring on using a xerogel or a fluorine resin in an inter level dielectric between the wirings to decrease a wiring capacitance, and the problem occurring on misalignment. A process for producing a semiconductor device comprising an inter level dielectric containing a xerogel film or a fluorine resin film comprises a step of forming, on the inter level dielectric comprising a lower layer of the inter level dielectric formed with an organic film and an upper layer of the inter level dielectric formed with a xerogel film or a fluorine resin film, a first mask to be an etching mask for forming a via contact hole by etching the inter level dielectric, and a step of forming, on the first mask, a second mask, which comprises a different material from the first mask, to be an etching mask for forming a wiring groove by etching the inter level dielectric.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates to a process for producing a semiconductor device, and more particularly, it relates to a process for producing a semiconductor device having a multi-layer wiring structure used for device process beyond the design rule of 0.25 μm.[0003]2. Description of the Related Art[0004]With the scale down of a semiconductor device, scale down of wiring and reduction of a wiring interval become necessary. Simultaneously, with the demand of low consuming electric power and high-speed operation, an inter level dielectric having a low dielectric constant and wiring having a low resistance become necessary. Particularly, in a logic device, because increase of the resistance and increase of the wiring capacitance due to the fine wiring bring about deterioration in operation speed, fine multi-layer wiring using a film having a low dielectric constant as an inter level dielectric becomes necessary.[0005]In or...

Claims

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Application Information

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Patent Type & Authority Patents(United States)
IPC IPC(8): H01L21/302H01L21/31H01L21/461H01L21/4763H01L21/3065H01L21/311H01L21/312H01L21/316H01L21/768
CPCH01L21/02118H01L21/0212H01L21/02126H01L21/022H01L21/02203H01L21/02274H01L21/02282H01L21/02304H01L21/31138H01L21/31144H01L21/76808H01L21/76811H01L21/76813H01L21/76829H01L21/76835H01L2221/1031H01L21/31695H01L21/3127
Inventor HASEGAWA, TOSHIAKITAGUCHI, MITSURUMIYATA, KOJI
Owner SONY CORP