Compact active pixel with low-noise image formation

Abstract

A low-noise active pixel circuit is disclosed that efficiently suppresses reset (kTC) noise by using a compact preamplifier consisting of a photodetector and only three transistors of identical polarity, in conjunction with ancillary circuits located on an imager's periphery. The use of only three transistors with a tapered reset signal allows the optical area to be increased, while still providing a low-noise imager.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates generally to electronic imaging devices and, more particularly, to low noise CMOS image sensors having increased optical area within each pixel.[0003]2. Description of the Related Art[0004]Significant advances in photosensor image processing for camera and video systems are now possible through the emergence of CMOS pixel sensors. CMOS-based imaging sensors have distinct manufacturing cost savings and consume much less power than other technologies such as charge coupled devices (CCD). A CMOS image sensor's performance, however, is often limited by the noise generated by resetting each of its photodiodes to a known potential after each electronic image, or picture, is read out. Such noise is readily suppressed in CCD-based cameras because CCD reset noise is generated on only one capacitance, i.e., the sense diffusion diode that converts the photo-generated charge to a voltage. Also, full-fr...

AI Technical Summary

Benefits of technology

The present invention is a low-noise imaging system that can be implemented in CMOS or other semiconductor fabrication technologies. It uses a compact preamplifier consisting of a photodetector and three transistors to efficiently suppress reset noise. The invention also includes supporting circuits to read the signal with low noise without having to perform correlated double sampling on either successive rows or the entire array. The invention is formed by the aggregate circuitry in each pixel, the supporting circuits in the column buffer amplifier and the row-based clock driver, and the waveform generation circuits servicing each column and row of pixels. The invention provides high sensitivity, minimizes demand on amplifier bandwidth, provides adequate power supply rejection, and is compatible with imaging arrays having pixel pitch to below 2.7 microns with high optical fill factor and low noise using 0.18 μm CMOS technology. The invention has the advantage of full process compatibility with standard silicided submicron CMOS, helps to maximize yield and minimize die cost because the circuit complexity is distributed amongst the active-pixels and peripheral circuits, and exploits the signal processing capability inherent to CMOS. The invention provides temporal read noise below 10 e−, fixed pattern noise significantly below 0.02% of the maximum signal, 1V signal swing for 3.3 V power supply, large charge-handling capacity, and variable sensitivity using simple serial interface updated on a frame-by-frame basis via digital interface to a host microprocessor.

Problems solved by technology

A CMOS image sensor's performance, however, is often limited by the noise generated by resetting each of its photodiodes to a known potential after each electronic image, or picture, is read out.

Similarly, the reset noise (kTC) in a CMOS sensor causes uncertainty about the voltage on each photodetector following the reset, but each pixel's reset signal is not normally available.

No CMOS foundry processes support integration of ITO electrodes due to possible wafer contamination and concomitant yield loss.

Another key issue related to incompatibility with standard CMOS technology is the difficulty in optically isolating this storage site to eliminate image smear.

The basic three transistor circuit thus generates large motion artifacts because of the need to successively read the reset and signal levels during each line of video.

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