Process for preparing isolation of shallow channel

Abstract

A manufacturing method of shallow groove insulation comprises providing a semiconductor substrate, positioning sequentially formed a pad oxide layer and a hard mask layer, forming a groove in the semiconductor substrate, arranging an opening in a position corresponding to the groove in the pad oxide layer and the hard mask layer, forming a medium layer in the groove and on the hard mask layer, removing the medium material on the hard mask layer by planarization technology, etching the medium layer in the groove to reduce the height difference between the medium layer surface and the semiconductor substrate surface, and lead the edge of the medium layer to form a protuberance. The manufacturing method of shallow groove insulation can reduce the depth of the top edge groove of the shallow groove insulation, and improve the element properties.

Description

technical field

[0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing shallow trench isolation (Shallow Trench Isolation, STI). Background technique

[0002] With the development of semiconductor manufacturing technology to high-tech nodes, the device-to-device isolation technology in semiconductor integrated circuits has also developed from the original Local Oxidation of Silicon (LOCOS) to shallow trench isolation. Shallow trench isolation is formed by forming a trench on a semiconductor substrate and filling the trench with a dielectric material. The Chinese patent application document with publication number CN 1649122A discloses a manufacturing method of shallow trench isolation. Figure 1 to Figure 5 It is a schematic cross-sectional view of the structure corresponding to each step of the manufacturing method of the shallow trench isolation disclosed in the Chinese patent application document. ...

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