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Semiconductor apparatus and method for fabricating the same

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve the problems of increased risk of dimensional changes, easy concentration of electric field, etc.

Inactive Publication Date: 2008-12-10
PS4 LUXCO SARL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

And, transistors fabricated in this state as Figure 20 As shown, the gate electrode 207 is embedded in the trench 205 via the gate insulating film 206 to form the transistor 201, so the electric field tends to concentrate in the trench upper portion 205a, and the risk of dimensional variation becomes large.
[0014] Moreover, if hydrogen baking (heating at about 900°C in a hydrogen atmosphere), such as Figure 18 As shown in (d), with the trench bottom 305b as a flat part, the Si flash can be basically completely removed, but the cross-sectional shape along the line A1-A1' is also close to a circle. After removing the mask and manufacturing the transistor, The electric field tends to concentrate on the upper part of the trench, and the risk of dimensional changes increases

Method used

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  • Semiconductor apparatus and method for fabricating the same
  • Semiconductor apparatus and method for fabricating the same
  • Semiconductor apparatus and method for fabricating the same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1、2

[0149] Optimum conditions for the photosensitive hydrogen bake and photosensitive DCE oxidation of the present invention were investigated for samples using hydrogen bake and oxidation method optimum conditions, producing Si flashes after silicon dry etching of trenches.

[0150] (sample construction)

[0151] The shape after dry etching is as follows Figure 5 the shape shown.

[0152] (Dry Etching Device)

[0153] A commercially available ICP plasma etching apparatus was used.

[0154] (Silicon dry etching conditions)

[0155] HBr / Cl 2 / O 2 =100 / 90 / 10sccm, 10mTorr (1.33Pa), RF (upper / lower)=500W / 100W (Stage temperature=10°C).

[0156] (Hydrogen baking reference conditions)

[0157] h 2 =15 L / min, 20Torr (2.67×10 3 Pa), 850°C, 600 sec.

[0158] The conditions required for hydrogen baking must meet the following two conditions at the same time:

[0159] (1) The height of Si flash is as low as about 20% of the initial height;

[0160] (2) The oxide film on the trenc...

Embodiment 3

[0178] Next, the optimum temperature and time conditions for the most effective DCE oxidation were investigated. Optimum time (50, 100, 150, 200 seconds) was studied in order to keep the temperature at 850° C., which is the lower limit set in the equipment used, so that the oxide film does not apply to the Si flash portion. The upper film thickness a', middle film thickness b', and bottom film thickness c' were measured, and their ratios (a' / b', b' / c') were calculated. The results are shown in Table 3.

[0179] table 3

[0180] Example 3

Comparative Example 8

Comparative Example 9

Comparative Example 10

Oxidation treatment time

(Second)

100

50

150

200

upper film thickness

(a')

1.5

1.0

1.8

2.1

Intermediate film thickness

(b')

1.3

0.85

15

1.8

Bottom Film Thic...

Embodiment 4

[0194] As a comparison with other processing methods, several methods were tried to remove the Si flash on the STI side generated in the dry etching process when trench gates are formed in DRAM, and their shapes were compared.

[0195] (sample construction)

[0196] The shape after dry etching is as follows Figure 5 the shape shown.

[0197] (Dry Etching Device)

[0198] A commercially available ICP plasma etching apparatus was used.

[0199] (Silicon dry etching conditions)

[0200] HBr / Cl 2 / O 2 =100 / 90 / 10sccm, 10mTorr (1.33Pa), RF (upper / lower)=500W / 100W (Stage temperature=10°C).

[0201] (Chemical Dry Etching Conditions)

[0202] CF 4 / Ar=100 / 100sccm, Pressure=20mTorr (2.67Pa), RF (upper / lower)=500W / 0W (Stage temperature=10°C).

[0203] (hydrogen bake only)

[0204] Hydrogen baking condition: H 2 =15 L / min, 20Torr (2.67×10 3 Pa), 875°C, 60sec.

[0205] (Method of the present invention: hydrogen baking+DCE oxidation)

[0206] Photosensitive hydrogen baking co...

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PUM

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Abstract

The invention provides a semiconductor device and a manufacturing method thereof. When rag generated by processing a groove is effectively removed at the same time of optimizing the shape of the groove, no parasitic groove and leaked current are generated. In such a semiconductor device, a groove (11) enables the section contour lines of a pair of second inner walls (11c) positioned at one side of an active area (K) and connected with an opening portion (11a) to form straight lines approximately, comprising the following process steps: a process step of removing the first rag, removing or reducing the rag (11e) through a hydrogen roasting process; a process step of forming a protective membrane, forming a protective membrane (14) on the surface of the groove (11) through an oxidization process; and a process step of removing the second rag, roasting the surface with the groove (11) of the protective membrane (14) by hydrogen, the section contour line of the second inner wall (11c) is approximately linear, and meanwhile further removing or reducing the residual rag (11e).

Description

technical field [0001] The present invention relates to a semiconductor device with a trench gate structure and a manufacturing method thereof. [0002] This application claims priority based on No. 2007-151597 filed in Japan on June 7, 2007, and thus the contents thereof are included in the present application. Background technique [0003] A semiconductor device generally has a structure in which an n-type diffusion layer, a gate insulating film, and a gate electrode are formed on the surface of a semiconductor substrate. ) effect becomes apparent. [0004] The short-channel effect means that when the gate length becomes shorter and the source electrode and the drain electrode are close together, since silicon is a highly conductive semiconductor, leakage occurs between the source and drain electrodes even when the gate is turned off. Current phenomenon (punch through). [0005] As a means of avoiding such short-channel effect problems, trench gate technology has drawn ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/10H01L29/423H01L29/78H01L21/336H01L21/302H01L21/28
CPCH01L21/823437H01L21/823481H01L29/4236H01L29/66621H10B12/053
Inventor 上田靖彦藤本紘行
Owner PS4 LUXCO SARL
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