Process for treating through wafer interconnection construction

Abstract

The invention discloses a through wafer interconnect structure processing method comprising: 1. etching a blind hole on a substrate; 2. etching a pattern dielectric substance layer on the substrate; 3. etching the pattern dielectric substance layer and the dielectric material at the bottom of the blind hole, keeping the dielectric material of a blind hole side wall; forming a dielectric substance hole on the substrate; 4. depositing a layer of conductive material on the dielectric substance hole and forming a conductive hole; 5. re-depositing a layer of pattern dielectric substance on the conductive layer and filling the conductive hole; 6. etching the back side of the plate to expose the conductive layer and forming a solder micro-convex point on the conductive layer, wherein the pattern dielectric substance material is preferable poly-p-xylene. The invention simplifies the process steps, reduces the process time and the cost; depresses a parasitic capacitance by using two layers of the pattern dielectric substance layers, improves a interconnect electrical behavior, suits for the high speed and RF three-dimensional interconnection structure; releases the thermal mismatch between the conductive material and the silicon and greatly reduces the thermal mechanical stress.

Description

technical field [0001] The invention belongs to an electrical interconnection processing technology in the field of very large-scale integrated circuit manufacturing, and is particularly suitable for processing system-in-package (SiP), system-on-chip (SoC) and through-silicon via (TSV) interconnection structures in the form of three-dimensional stacking. technical background [0002] In the past forty years, the research, development and production of microelectronic components have been carried out in the direction predicted by Moore's law. In 2008, Intel and several other companies have begun to use 45 to 50 nanometer processing technology in the mass production of memory chips. According to this development trend, by 2012 at the latest, in order to further improve the integration of chips, 32 or even 22 nanometer processing technology will be required. However, the processing technology of 32 or 22 nanometers not only encounters the limitations of lithography equipment a...

AI Technical Summary

Problems solved by technology

[0005] This process flow can effectively realize high-density three-dimensional through-hole interconnection, but there are the following problems: (1) there is only a very thin insulating layer (usually silicon dioxide) between the silicon substrate and the copper structure layer , which leads to the formation of high capacitance between TSV interconnects, sometimes even exceeding the capacitance of standard wire-bonded interconnects; (2) fairly thick copper structures are filled in silicon holes

Due to the large thermal mismatch between silicon and copper, this will cause significant thermomechanical stress during thermal cycling; (3) the method of fully filling silicon holes with electroplated copper requires a long man-hour, which increases the process method cost

Images