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64results about How to "Reduce thermomechanical stress" patented technology

Production method for through wafer interconnection construction

The invention discloses a through wafer interconnect structure preparation method comprising: 1. bonding a bonding silicon device wafer on a silicon wafer substrate; 2. thinning the silicon device wafer, etching the silicon device and forming a blind hole; 3. coating a layer of pattern dielectric material (such as poly-p-xylene) on the silicon device wafer; 4. etching the pattern dielectric substance layer, etching the dielectric material at the bottom of the blind hole, keeping a blind hole side wall; forming a dielectric substance hole on the substrate and enabling the dielectric substance hole and the blind hole coaxial; 5. depositing a layer of conductive material on the dielectric substance hole as a conductive layer and forming a conductive hole; 6. re-depositing a layer of pattern dielectric substance on the conductive layer; 7. forming a solder micro-convex point on the conductive layer. The invention simplifies the process steps, reduces the process time and the cost; depresses a parasitic capacitance, improves a interconnect electrical behavior, suits for the RF three-dimensional interconnection structure; releases the thermal mismatch between the conductive material and the silicon and greatly reduces the thermal mechanical stress.
Owner:HUAZHONG UNIV OF SCI & TECH

Packaging structure and packaging method of semiconductor device

The invention discloses a packaging structure and a packaging method of a semiconductor device. The packaging structure of the semiconductor comprises a chip, a passivation layer positioned above the chip, a pad positioned above the passivation layer, a first through hole running through the chip and the passivation layer along a thickness direction to the outside of the pad, a seed crystal layer positioned in the inner wall of the first through hole, a conductor layer positioned on the seed crystal layer, a conductive layer filling up the first through hole, a second through hole, an insulating medium layer, a convex point lower metal layer and convex points, wherein the seed crystal layer, the conductor layer and the conductive layer in the first hole form a first conductive plug; the second through hole runs through the chip and the passivation layer along the thickness direction to the outside of the pad, is positioned around the first through hole and shares a side wall with the first through hole; the insulating medium layer is positioned above the chip, fills up the second through hole and is exposed out of the first conductive plug; the convex point lower metal layer is positioned on the insulating medium layer on the first conductive plug and the periphery of the conductive plug; and the convex points are on the convex point lower metal layer. In the packaging structure and the packaging method, ultra high capacitance caused by TSV interconnection is avoided and the electrical property of the semiconductor packaging structure is improved.
Owner:CHINA WAFER LEVEL CSP
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