Circuit device three-dimensional integrative method

Abstract

The invention discloses a circuit device three-dimensional integrative method, which comprises the following steps of: manufacturing a blind hole on the front side of a first substrate disc with the circuit device; bonding the front side of a first substrate disc and an auxiliary disc, carrying out back reduction processing on the first substrate disc, and causing an open mouth of the blind hole to form a through hole; using a metal seed layer on the auxiliary disc as a starting point and filling an electric conduction metal in the through hole in an electro-plating mode from bottom to top; and bonding the back side of the first substrate disc and the front side of a second substrate disc with the circuit device. In the embodiment of the invention, when the circuit device is integrated ina three-dimensional way, the blind hole is manufactured in the substrate disc with the circuit device and opened to form the through hole, and the metal is filled in the through hole by using the auxiliary disc in the electro-plating mode from bottom to top, thus avoiding a hole and a gap appearing on the electro-plated bind hole, realizing the three-dimensional interconnection of high density andhigh aspect ratio, and simultaneously reducing the technology difficulty of the three-dimensional integration and interconnection.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a method for three-dimensional integration of circuit devices. Background technique [0002] Circuit devices, such as integrated circuits, sensors and MEMS (Micro-Electro-Mechanical System), have now developed to the stage of system-on-a-chip (SOC, System on a Chip), and the production of system-on-chip is adopted Technology can realize all the functions of the system on a single chip. One of the difficulties in the development of SOC is the compatibility of different manufacturing processes. In the process of making SOC, it may be necessary to use a variety of standard manufacturing processes, but the manufacturing methods and adoption of these manufacturing processes The substrate materials are different, and it is difficult to implement them on the same chip. Even if the substrate materials are the same, the manufacturing feasibility of each circuit module must ...

AI Technical Summary

Problems solved by technology

[0006] After researching the existing technology, the inventors found that, based on the realization of the blind hole, since only Damascus plating can be used, it is easy to make the blind hole be sealed at the opening first, forming a hole inside the filled metal line

In order to ensure the reliability of the three-dimensional interconnection, the blind holes made on the substrate cannot be too deep, so the aspect ratio of realizing the three-dimensional interconnection of the substrate wafer is very limited

It is easy to fill the through-holes based on the implementation of through-holes, but in order to ensure the operability on the substrate wafer, the thickness of the single-layer substrate wafer often exceeds 200 microns. Although it has a high aspect ratio, it also limits Increased interconnect density

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