Composite plane terminal passivating method for controllable silicon device

Abstract

The invention relates to a composite plane terminal passivating method for a controllable silicon device. The method comprises the following processes: 1, pushing phosphorus atoms into a silicon chip in a certain depth under certain temperature, time and atmosphere to form a gate region so as to finish oxidation and diffusion of a cathode region of the chip; 2, fully peeling an oxidation layer onthe surface of the silicon chip to form a chip silicon substrate layer; 3, depositing a passivation layer on the surface of the chip silicon substrate layer formed in the step 2; 4, depositing a first protective layer, a second protective layer and a third protective layer on the surface of the passivation layer formed in the step 3 in turn to form a passivating film protective PN junction terminal; and 5, annealing the passivating film protective PN junction terminal formed in the step 4 for certain time, and engraving a cathode and gate pole lead hole window at the passivating film protective PN junction terminal through photo-etching so as to finish passivation of the controllable silicon plane terminal. The method can improve the parameter stability and controllability of a controllable silicon product, reduce the area of the chip, shorten the production flow, reduce the fragment rate and reduce the production cost.

Description

(1) Technical field [0001] The invention relates to a plane processing method of a thyristor device. It belongs to the technical field of discrete device processing technology. (2) Background technology [0002] In recent years, the demand for consumable products of thyristor devices has increased greatly, and their types have also increased accordingly, and product competition has become increasingly fierce. How to improve parameter consistency, reduce fragmentation rate, and reduce production cost under the condition of ensuring reliability has become the goal pursued by chip manufacturers. [0003] Before the present invention was made, shallow mesa technology was widely used in the production field of thyristor devices. Its processing technology is as follows: [0004] Step 1. Under a certain temperature, time and atmosphere, push phosphorus atoms to a certain depth on the surface of the silicon wafer to form a gate area, such as figure 1 shown. [0005] Step 2, car...

AI Technical Summary

Problems solved by technology

[0010] 1. The terminal passivation process of the countertop process is cumbersome

[0011] Although the countertop technology is relatively mature, the process is very complicated and requires groove photolithography, glass electrophoresis, glass sintering, glass protection, and glass reverse etching

[0012] 2. High fragmentation rate of countertop technology: 10%-20%

[0014] 3. The consistency of the process parameters of the table is poor, and the gate trigger current (I GT ), off-state repetitive peak voltage (V DRM ) is difficult to guarantee

[0015] The mesa process relies on glass passivation to ensure the breakover voltage, and glass is easily corroded. Once there is a problem with the protective layer, the chip is easily scrapped

[0016] 4. The structure design of the mesa terminal accounts for a large proportion of the chip area

[0017] In summary, the disadvantages of the mesa passivation process are that the processing process is complex, parameter control is difficult, the chip is fragile after the silicon etching groove is filled with glass, and the mesa terminal structure occupies a much larger proportion of the chip area than the planar process.

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