Modeling method of phase shift mask in photolithographic process

Abstract

The invention belongs to the field of integrate circuit photolithography, relating to a modeling method for processing phase shift mask in parallel. In the method, the mask is divided into N numbered vertical reticle mask structures along the longitudinal direction on the vertical juncture of the metal and the quartz of the mask to cause the dielectric constant of the adjacent vertical reticle mask structure to have different distributions on the vertical direction. The characteristic function and the characteristic value of the electric field of the characteristic vertical reticle mask structure are calculated with a spectral element method based on non-continuous Galerkin, and serve as the electric component of the vertical reticle mask structure represented by the primary function; in the horizontal direction, Schwartz iteration is adopted to solve the electric field equation and the boundary condition of N numbered vertical reticle mask structures; in each iteration, the electric field calculation task of N numbered vertical reticle mask structures is distributed to a plurality of calculation nodes to be finished in parallel; and the left and right boundary conditions of each vertical reticle mask structure adopt the solution of the adjacent vertical reticle mask structure in the previous step. The invention has the characteristics of high precision and parallel calculation and can handle the modeling of the practical large-scale phase shift mask of any structure.

Description

technical field [0001] The invention belongs to the field of photolithography of integrated circuits, relates to a photolithography process in the manufacture of integrated circuits, and in particular relates to a novel method for parallel processing phase-shift mask modeling. Background technique [0002] The lithography process is the core technology in the integrated circuit manufacturing process. It realizes the imaging of the design pattern on the semiconductor silicon wafer through the lithography machine system. As the integrated circuit manufacturing process enters the nanometer era, the feature size of the chip is reduced to 65nm, 45nm, 32nm and even 22nm, but the high development cost makes the lithography process still use the large-scale light wave of 193nm. Since the feature size of integrated circuit devices and interconnection lines is smaller than the wavelength of the light source, the significant interference and diffraction effects of large-scale light wav...

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Problems solved by technology

The waveguide method also has some shortcomings. First, the Fourier series expansion is used to make the area to be solved be extended periodically. Since the actual problem to be solved is not periodic, the calculation area must be expanded several times to make the solution of the area to be solved as possible. It is less affected by period extension; secondly, the dielectric material of the mask (such as chrome (chrome) and quartz (quartz)) presents a step change, and the approximation of the dielectric constant distribution of the step requires a high-order Fourier series. On the one hand, it increases the computational complexity. On the other hand, the finite truncation of the Fourier series brings about the Gibbs effect, which affects the calculation accuracy of the electromagnetic field at the step.

Another major problem with the above three methods is that they can only model small-scale reticles and cannot analyze and model actual large-scale reticles, which seriously restricts the practical application of the above three methods

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