High-voltage low-on-resistance LDMOS device and manufacturing method thereof

Abstract

The invention relates to a high-voltage low-on-resistance lateral double-diffusion metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The high-voltage low-on-resistance LDMOS device comprises P-epitaxy, a P-well region, an N+ anode, an N+ cathode, a P+ cathode end, an anode multi-crystal field board, a cathode multi-crystal field board, gate polycrystal, a gate oxide, a field oxide layer, a P-substrate, an N-well region and a P-type region, and also comprises the P-type region and a P-buried layer, wherein the P-type region is positioned on the surface of the N-well region; and the P-buried layer is positioned in the N-well region; the P-type region is isolated from the P-well region and the N+ anode, the P-type region is isolated from the field oxide layer; the P-type region and the N-well region form a PN junction; and the N-well region is segmented into a second N-well region and a first N-well region which are positioned above the P-buried layer by using the P-buried layer; and the P-buried layer forms PN junctions with the first N-well region and the second N-well region respectively. The high-voltage low-on-resistance LDMOS device has the advantages that: on one hand, the compatibility of the LDMOS device and a conventional low-voltage Bipolar+metal oxide semiconductor (CMOS)+double-diffusion metal-oxide-semiconductor (DMOS) (BCD) process is improved, on the other hand, the on-resistance of the LDMOS device is reduced on the premise of the same voltage resistance.

Description

technical field [0001] The invention relates to semiconductor high-voltage and low-resistance devices in the field of electronic technology, in particular to high-voltage power devices manufactured on bulk silicon. Background technique [0002] LDMOS devices are high-voltage power devices, which have the characteristics of high operating voltage, relatively simple process, and high switching frequency, and the processing technology based on bulk silicon materials is relatively mature, so LDMOS devices have broad development prospects. The drain, source and gate of the LDMOS device are all located on its surface, which is easy to integrate into the chip, so it is especially suitable as a high-voltage power device in high-voltage integrated circuits (HVIC) and power integrated circuits. Since J.A. Appels proposed the famous RESURF (Reduced Surface Field) principle in 1979, LDMOS devices have developed rapidly. [0003] A conventional LDMOS device in the prior art such as fig...

AI Technical Summary

Problems solved by technology

The SINGLE / DOUBLE-RESURF LDMOS devices in the prior art all use a single well process to manufacture the N-well region 16, which is the drift region of the LDMOS device. Because the junction depth of the drift region is very deep, its fabrication takes a long time The high-temperature thermal process has high requirements on the process, thus increasing the cost of the chip

In addition, due to the short well push time of the conventional medium and low voltage BCD process, the manufacturing process of the drift region of the LDMOS device in the prior art is not compatible with the conventional medium and low voltage BCD process.

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