Integrated circuit parallel testing method, device and system

Abstract

The invention discloses an integrated circuit testing method, device and system. A common substrate comprises a plurality of units to be tested and a plurality of operation result comparison devices for the units to be tested, wherein different units to be tested execute same input excitation and generate respective operation results, the operation results are compared by the corresponding operation result comparison devices to generate comparison features, and invalid tested units are detected according to the features. According to the invention, the testing cost can be reduced, the time for forming scale mass production can be shortened, and the missing rate is decreased.

Description

technical field [0001] The invention belongs to the field of integrated circuits, in particular to a parallel testing method, device and system for integrated circuits. Background technique [0002] A typical semiconductor fabrication process is to fabricate multiple identical rectangular dies on a thin, uniform wafer of semiconductor material. The grains are separated by scribe lines with a width of 60-80 microns. Mask alignment marks and wafer acceptance test (WAT) test elements are often placed on the dicing lanes to monitor quality during production. [0003] During the manufacturing process, the photolithography machine exposes one area at a time, called a stepper field, and each photolithography area contains one or more crystal grains. When all fabrication steps are complete, each die on the wafer must pass functional testing. Wafer test equipment (wafer prober) uses a probe card to contact the pad of the die to be tested, and transmits the test stimulus generated ...

AI Technical Summary

Problems solved by technology

[0013] To sum up, the existing integrated circuit testing methods, devices and systems, due to the limitation of the number of test channels, can only test one or several units under test at a time, and cannot achieve large-scale simultaneous / parallel comparison of the units under test.

The limited number of test channels is the bottleneck restricting the improvement of test efficiency

Images