Semiconductor component packaging structure and manufacturing method thereof
A technology of packaging structure and manufacturing method, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of increased cost, difficulty in controlling the surface of crystal grains at the same level, etc. effect of grain displacement, improved mechanical reliability, and increased packaging productivity
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[0072] The present invention will be described with preferred embodiments and accompanying drawings. It must be understood, however, that these referenced embodiments of the invention are for illustration purposes only. In addition to the preferred embodiments mentioned here, the present invention can be widely practiced in other embodiments.
[0073] The present invention discloses a crystal grain or multi-chip embedded substrate structure; the substrate has dual built up layers covering two surfaces. Figure 12To illustrate a cross-sectional view of a system in package (system in package) structure, the above-mentioned substrate has a die-embedded structure, double side build uplayers, passive components, wafer level chip size package structure (wafer level chip scale package, WL-CSP), chip scale package structure (chip scale package, CSP), ball grid array (ball gridarray, BGA) and flip-chip (flip-chip), etc. According to the teachings of the present invention, the surface...
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