Transverse diffusion metal oxide semiconductor (MOS) device with low on-resistance

Abstract

The invention discloses a transverse diffusion metal oxide semiconductor (MOS) device with low on-resistance. The device comprises a P-type well layer and an N-type lightly doped layer which are positioned in a P-type substrate layer, wherein a gate oxide layer is arranged above the P-type well layer in an area between a source area and the N-type lightly doped layer; at least two grooves are formed on the upper part of the P-type well layer between the source area and the N-type lightly doped layer, and the etching depth of the grooves is between one fourth and one fifth of the junction depth of the source area; the N-type lightly doped layer consists of a first N-type lightly doped area, a second N-type lightly doped area and a P-type lightly doped area; the doping concentration of the first N-type lightly doped area is higher than that of the P-type lightly doped area, and the doping concentration of the P-type lightly doped area is higher than that of the second N-type lightly doped area; and the proportional range of the doping concentrations of the first N-type lightly doped area and the second N-type lightly doped area is 1.2:1-1.3:1. According to the power MOS device with the low on-resistance, the volume of the device is reduced, the response time of the device is shortened, the frequency characteristic of the device is improved, and the long-term stability of the performance parameter of the device is achieved.

Description

technical field [0001] The invention relates to a MOS device, in particular to a metal oxide power MOS semiconductor device. Background technique [0002] Metal oxide power MOS semiconductor devices, with the rapid development of the semiconductor industry, power electronics technology represented by high-power semiconductor devices has developed rapidly, and its application fields have continued to expand, such as the control of AC motors and printer drive circuits. Among various power devices today, the laterally diffused MOS semiconductor device LDMOS has a high operating voltage and a relatively simple process, so LDMOS has broad development prospects. In the design of LDMOS devices, the breakdown voltage and on-resistance have always been the main goals that people pay attention to when designing such devices. The thickness of the epitaxial layer, doping concentration, and the length of the drift region are the most important parameters of LDMOS. The breakdown voltage ...

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Problems solved by technology

[0003] With the development of device miniaturization, the existing LDMOS design occupies a large layout area, which is not conducive to its integration with other functional devices to further reduce the volume and expand the application range. Therefore, how to design a device that can effectively reduce the current Some LDMOS occupy the surface area of ​​the silicon wafer and can further improve the performance of the device, becoming a technical obstacle

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