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Crystal face selection-based dual-strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and preparation method

An integrated device, dual-strain technology, applied in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc., can solve problems such as limitations, mobility cannot be optimized at the same time, and carrier material mobility of Si material is low.

Inactive Publication Date: 2012-10-24
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At the same time, NMOS devices and PMOS devices are prepared on the same crystal plane, and their mobility cannot be optimized at the same time.
[0007] Due to the low mobility of Si materials, the performance of integrated circuits manufactured using Si BiCMOS technology, especially the frequency performance, is greatly limited; for SiGe BiCMOS technology, although the bipolar transistor uses SiGe HBT devices , but Si CMOS is still used for unipolar devices that restrict the improvement of the frequency characteristics of BiCMOS integrated circuits, so these limit the further improvement of the performance of BiCMOS integrated circuits

Method used

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  • Crystal face selection-based dual-strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and preparation method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0120] Embodiment 1: Preparation of 22nm double-strained BiCMOS integrated device and circuit based on crystal plane selection, the specific steps are as follows:

[0121] Step 1, SOI substrate material preparation.

[0122] (1a) Select the N-type doping concentration as 1×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0123] (1b) Select the P-type doping concentration as 1×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.5 μm, which is used as the base material of the lower layer;

[0124] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the lower layer and the upper layer of substrate material after hydrogen injection;

[0125] (1d) SiO on the surface of the lower and upper su...

Embodiment 2

[0189] Embodiment 2: Preparation of 30nm double-strained BiCMOS integrated device and circuit based on crystal plane selection, the specific steps are as follows:

[0190] Step 1, SOI substrate material preparation.

[0191] (1a) Select the N-type doping concentration as 3×10 15 cm -3 The Si wafer with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0192] (1b) Select the P-type doping concentration as 3×10 15 cm -3 The Si sheet with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 0.75 μm, which is used as the base material of the lower layer;

[0193] (1c) Using a chemical mechanical polishing (CMP) process to polish the surface of the substrate material of the lower layer and the upper layer of the active layer after injecting hydrogen, respectively;

[0194] (1d) SiO ...

Embodiment 3

[0258] Embodiment 3: Preparation of 45nm double-strained BiCMOS integrated device and circuit based on crystal plane selection, the specific steps are as follows:

[0259] Step 1, SOI substrate material preparation.

[0260] (1a) Select the N-type doping concentration as 5×10 15 cm -3 The Si sheet with a crystal plane of (110) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the upper layer, and hydrogen is injected into the base material;

[0261] (1b) Select the P-type doping concentration as 5×10 15 cm -3 The Si wafer with a crystal plane of (100) is oxidized on the surface, and the thickness of the oxide layer is 1 μm, which is used as the base material of the lower layer;

[0262] (1c) Using a chemical mechanical polishing (CMP) process to polish the lower layer and the surface of the upper substrate material after hydrogen injection;

[0263] (1d) SiO on the surface of the lower and upper substrate mater...

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Abstract

The invention discloses a crystal face selection-based dual-strain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) integrated device and a preparation method thereof. The preparation method comprises the steps of: growing N-Si on a Si substrate to be used as a bipolar device collector region, photoetching a base region, growing P-SiGe, i-Si and i-Poly-Si on the base region, preparing a deep channel for isolation, preparing an emitter electrode, a base electrode and a collector electrode to form a SiGe HBT (Heterojunction Bipolar Transistor) device; etching a deep channel on an NMOS device region, growing a strain Si epitaxial layer selectively along a crystal face (100), preparing a strain Si channel NMOS (N-channel Metal Oxide Semiconductor) device on the NMOS device region; and growing a strain SiGe epitaxial layer selectively along a crystal face (110) on a PMOS (P-channel Metal Oxide Semiconductor) device active region, and preparing a PMOS device on the PMOS device active region. According to the invention, by using the characteristics that an electronic drift mobility of a tensile strain Si material is higher than that of a body Si material and a hole drift mobility of a compressive strain SiGe material is higher than that of the body Si material, and the influence of the crystal faces on the electronic drift mobility, the dual-strain BiCMOS integrated device and a circuit with enhanced properties are prepared.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a dual-strain BiCMOS integrated device with crystal plane selection and a preparation method. Background technique [0002] In the contemporary era of highly developed information technology, microelectronic technology represented by integrated circuits is the key to information technology. As the fastest-growing, most influential and most widely used technology in human history, integrated circuits have become an important symbol to measure a country's scientific and technological level, comprehensive national strength and national defense strength. [0003] "Moore's Law", which has had a huge impact on the development of the microelectronics industry, states that the number of transistors on an integrated circuit chip doubles approximately every 18 months, and the performance also doubles. For more than 40 years, the world's microelectroni...

Claims

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Application Information

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IPC IPC(8): H01L27/06H01L21/8249
Inventor 张鹤鸣宋建军王海栋王斌胡辉勇宣荣喜舒斌郝跃
Owner XIDIAN UNIV