Check patentability & draft patents in minutes with Patsnap Eureka AI!

Split gate flash memory embedded in logical circuit and method for manufacturing memory set

A technology for separating gates and manufacturing methods, applied in circuits, semiconductor/solid-state device manufacturing, electrical components, etc., can solve problems such as memory operating speed signal transmission bandwidth limitations, etc., to achieve increased density, reduced costs, and small integrated chips. Effect

Active Publication Date: 2014-07-30
SEMICON MFG INT (SHANGHAI) CORP
View PDF3 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] If split-gate flash memory, high-voltage transistors, and logic transistors are all built on discrete integrated chips, the operating speed of the entire memory will be limited by the signal transmission bandwidth between the flash memory and peripheral circuits

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Split gate flash memory embedded in logical circuit and method for manufacturing memory set
  • Split gate flash memory embedded in logical circuit and method for manufacturing memory set
  • Split gate flash memory embedded in logical circuit and method for manufacturing memory set

Examples

Experimental program
Comparison scheme
Effect test

no. 1 example

[0069] refer to figure 1 The flow shown specifically introduces the manufacturing method of the split-gate flash memory embedded in the logic circuit provided by the specific embodiment of the present invention. The split-gate flash memory embedded in the logic circuit includes three regions, the first region It is a split-gate flash memory, the second area is a high-voltage transistor, and the third area is a logic transistor. It should be noted that the second area where the high-voltage transistor is located and the third area where the logic transistor is located are both located in the peripheral circuit area in the actual layout, therefore, the positional relationship between the high-voltage transistor and the logic transistor is not affected by the diagram provided in the first embodiment. limits.

[0070] Firstly, step S11 is performed to provide a semiconductor substrate 11, the structural cross-sectional view of which is shown in figure 2 As shown, the semiconduc...

no. 2 example

[0088] Figure 16 Shown is a flow chart of a manufacturing method of a split-gate flash memory group embedded with logic circuits according to the second embodiment of the present invention. The group of split-gate flash memories embedded with logic circuits includes a pair of split-gate flash memories embedded with logic circuits of the same size, and each pair of split-gate flash memories embedded with logic circuits includes: Gate flash memory, high voltage transistors, logic transistors. The fabrication method below takes a pair of split-gate flash memories embedded with logic circuits as an example. Same as the first embodiment, the split-gate flash memory with erase gate and word line gate is still taken as an example.

[0089] Step S11' is executed to provide a semiconductor substrate 11', which includes six regions for forming a pair of identical split-gate flash memories embedded with logic circuits, such as Figure 17 As shown, the six regions are specifically: th...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention provides a method for manufacturing a split gate flash memory embedded in a logical circuit. Compared with a method for forming a single split gate flash memory, the method for manufacturing the split gate flash memory embedded in the logical circuit includes the steps of precipitating polycrystalline silicon once, precipitating silicon oxide once, etching twice, and covering with fluid material once. The invention further provides a method for manufacturing a split gate flash memory set embedded in the logical circuit. According to the technical scheme of the method, the split gate flash memory, a high voltage transistor and a logic transistor can be manufactured on one integrated circuit. The split gate flash memory, the high voltage transistor and the logic transistor manufactured by the method are high in density, integration degree and running speed, and meanwhile, integrated chips are smaller, thus cost for each integrated chip is lowered, and application range is wider. In addition, during the manufacturing of the split gate flash memory, gates of the high voltage transistor and the logic transistor are not subjected to etching, so that the high voltage transistor and the logic transistor have fewer defects, and requirements on gate quality can be met.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a split-gate flash memory embedded in a logic circuit and a manufacturing method of a split-gate flash memory group embedded in a logic circuit. Background technique [0002] Random access memory, such as DRAM and SRAM, has the problem of data loss after power failure during use. To overcome this problem, various nonvolatile memories have been designed and developed. Recently, flash memory based on the floating gate concept has become the most versatile non-volatile memory due to its small cell size and good performance. The non-volatile memory mainly includes two basic structures: a stack gate structure and a split gate structure. The stacked gate structure memory includes a tunnel oxide layer formed on the substrate, a floating gate polysilicon layer (ploy 1) for storing electrons, an oxide / nitride / oxide (oxide-nitride-oxide, ONO ) stack and control gate polysilicon l...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H01L21/8234
Inventor 王友臻周儒领
Owner SEMICON MFG INT (SHANGHAI) CORP
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More