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Semiconductor devices with 2DEG and 2DHG

A semiconductor and device technology, applied in the field of semiconductor devices, can solve the problems that the concept of super junction cannot be realized by Group III nitride semiconductors, p-type doping cannot be generated, etc.

Active Publication Date: 2013-05-08
UNIV OF SHEFFIELD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the superjunction concept has not yet been realized in Group III nitride semiconductors because the doping of the semiconductor cannot be controlled with sufficient precision at present.
In fact, in general, p-type doping cannot be successfully produced in Group III nitride semiconductor devices

Method used

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  • Semiconductor devices with 2DEG and 2DHG
  • Semiconductor devices with 2DEG and 2DHG
  • Semiconductor devices with 2DEG and 2DHG

Examples

Experimental program
Comparison scheme
Effect test

no. 1 approach ( 2

[0058] First embodiment (two-dimensional hole-gas superjunction Schottky barrier diode (2DHG SJ SBD))

[0059] refer to figure 1 , according to one embodiment of the present invention, a Schottky barrier diode (SBD) 100 includes a substrate 105 on which three Group III nitride semiconductor layers 110 , 115 , 120 are grown. Three electrodes 125 , 130 , 135 are formed on the semiconductor layers 110 , 115 , 120 .

[0060] An undoped gallium nitride (u-GaN) layer 110 is provided directly onto the substrate 105 . An undoped aluminum gallium nitride (u-AlGaN) layer 115 is disposed on the first u-GaN layer 110 to form a movable Two-dimensional electron gas (2DEG) 145 . The third layer 120 including the second u-GaN layer is located on the u-AlGaN layer 115, thereby inducing two-dimensional hole gas (2DHG) at the heterojunction interface between the u-AlGaN layer 115 and the third layer 120 150. The two-dimensional hole gas 150 is a planar region or layer with a majority of p-ty...

no. 2 approach

[0067] refer to figure 2 , the depletion-type p-channel transistor 200 according to the second embodiment of the present invention is made of a wafer having the structure as described above according to the first embodiment. In this embodiment the corresponding wafer layers will be referenced by the reference numerals of the first embodiment, but increased by 100. Thus, the transistor 200 includes a substrate 205 on which the Group III nitride semiconductor layers 210, 215, 220 are grown. Four electrodes 225 , 230 , 235 , 240 are formed on the semiconductor layers 210 , 215 , 220 .

[0068] Three electrodes - the drain 225 , the gate 230 and the source 235 - are arranged on top of the third layer 220 . Both the drain 225 and the source 235 are formed of a metal with a work function that allows an ohmic connection to the 2DHG 250 . Third layer 220 is thin enough to allow drain 225 and source 235 to be electrically connected to 2DHG 250 through respective ohmic current paths...

no. 3 approach

[0078] now refer to image 3 , the enhancement type p-channel transistor 300 according to the third embodiment of the present invention is made of a wafer having the structure as described above according to the first embodiment. In this embodiment the corresponding wafer layers will be referenced by the reference numerals of the first embodiment, but increased by 200. Accordingly, the transistor 300 includes a substrate 305 and Group III nitride semiconductor layers 310 , 315 , 320 . Four electrodes 325 , 330 , 335 , 340 are formed on the semiconductor layers 310 , 315 , 320 .

[0079] Two electrodes - a drain 325 and a source 335 - are disposed on top of the third layer 320 . Source 335 and drain 325 are each formed of a metal having a work function that allows ohmic connection to 2DHG 350 . The third layer 320 is thin enough to allow the drain 325 and source 335 to be electrically connected to the 2DHG 350 through respective ohmic current paths 325a, 335a.

[0080] A no...

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PUM

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Abstract

A semiconductor device comprises three semiconductor layers. The semiconductor layers are arranged to form a 2DHG and a 2DEG separated by a polarization layer. The device comprises a plurality of electrodes: first and second electrodes electrically connected to the 2DHG so that current can flow between them via the 2DHG and a third electrode electrically connected to the 2DEG so that when a positive voltage is applied to the third electrode, with respect to at least one of the other electrodes, the 2DEG and the 2DHG will be at least partially depleted.

Description

technical field [0001] The present invention relates to a semiconductor device, in particular, to a semiconductor device including two-dimensional hole gas and utilizing the concept of a super junction. Background technique [0002] In silicon, the superjunction (SJ) concept applies stacked layers alternately doped with p-type or n-type dopants so that the charge in one layer is compensated by the opposite polarity charge in the next layer to A high overall charge density is achieved. This requires precise doping. Superjunctions based on power field effect transistors are commercially available today. [0003] Group III nitride semiconductors are considered to be excellent candidates for next-generation power devices. Group III nitride semiconductors have a high electron saturation velocity, a high breakdown field strength, and a wide energy band gap, and can provide a heterojunction. However, the superjunction concept has not yet been realized in Group III nitride semic...

Claims

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Application Information

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IPC IPC(8): H01L29/872H01L29/778H01L29/10H01L27/095
CPCH01L29/7787H01L29/7786H01L29/2003H01L29/1029H01L29/872H01L29/7782H01L27/095H01L29/42316H01L29/12H01L29/7783H01L29/778H01L29/10H01L29/782
Inventor A·中岛S·N·E·马达蒂尔
Owner UNIV OF SHEFFIELD
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