Method for growing Gaas material hemt device in art structure trench

Abstract

The invention discloses a method of growing a high electron mobility transistor (HEMT) device of GaAs materials in an ART-structure groove. The method comprises the following steps. A silica layer is grown on a silicon substrate, and a plurality of grooves are etched on the silica layer along the direction of the silicon substrate (110) through holographic exposure and an inductively coupled plasma (CIP) method. Piranha, SC2, HF and deionized water are respectively used for cleaning. The rest silica layer at the bottoms of the grooves is removed, and the silicon substrate is exposed. A metal organic chemical vapor deposition (MOCVD) method is utilized so that a buffering layer, a superlattice buffering layer, a channel layer, an isolating layer, an N-shaped heavy doping electronic supplying layer and a cover layer are sequentially and slowly grown on the silicon substrate in the grooves. A chemical polishing method is utilized for polishing the cover layer, and roughness of the cover layer after polishing is less than 1nm. By the crafts of photoetching, corrosion and metal wiring, a source electrode, a drain electrode and a grid electrode are formed on the cover layer after the cover layer is polished along the direction of the grooves, and manufacture of the device is finished. By changing raw materials, adding the superlattice buffering layer and combining high aspect ratio groove limiting technology, adaptive dislocation of an interface and extension to an outer layer of amplitude probability distribution (APD) are restrained.

Description

technical field [0001] The invention relates to a method combining MOCVD and a high aspect ratio trench confinement technology (AspectRatioTrapping, ART), in particular to a method for growing a GaAs material HEMT device in a trench with an ART structure. Background technique [0002] According to the forecast of the International Semiconductor Industry Technology Development Blueprint (ITRS2009), the physical gate length of the MPU will be reduced to 22 nanometers in 2012. However, with the development of integrated circuit technology below the 22nm technology node, silicon integrated circuit technology is limited by a series of basic physical problems and process technology in terms of speed, power consumption, integration, reliability, etc., and expensive production lines Construction and manufacturing costs make the integrated circuit industry face huge investment risks, and the traditional silicon CMOS technology adopts "downscaling" to achieve smaller, faster, and chea...

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Problems solved by technology

These dislocations and antiphase domain boundaries will extend all the way to the surface of the epitaxial layer, seriously affecting the quality of the epitaxial layer

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