NOR structure flash memory and manufacturing method thereof

Abstract

The present invention relates to the technical field of flash memories, and provides a NOR structure flash memory and a manufacturing method thereof. In the manufacturing method, a mask dielectric layer is formed and covered on a second polysilicon layer of a gate laminated structure, a part of the mask dielectric layer is patterned and etched to expose a part of the second polysilicon layer on one side that is relatively closer to a source of the NOR structure flash memory, and self-alignment is performed on the exposed second polysilicon layer to form a metal silicide layer. Therefore, in the manufactured NOR structure flash memory, the mask dielectric layer that is not etched can be approximately disposed between the metal silicide layer and a drain contact hole of the NOR structure flash memory. The leakage current between the gate and the drain of the NOR structure flash memory is small, the processing procedure of the manufacturing method is not complex, the process window is large, the side effect is small, and the feasibility of large-scale production is high.

Description

technical field [0001] The invention belongs to the technical field of flash memory (Flash Memory), and relates to a flash memory with a NOR (EPROM Tunnel Oxide, EPROM tunnel oxide layer) structure and a preparation method thereof. Background technique [0002] Flash memory is a common memory that has been widely used in various digital storage fields. Flash memory usually implements information storage through a floating gate (Floating Gate) structure. According to differences in floating gate structures, various types of flash memory have been developed so far. Among them, the NOR structure flash memory is an important flash memory. The ETOX? NOR structure flash memory launched by Intel Corporation in the last century also occupies a large market share in the memory market. [0003] figure 1 Shown is a schematic structural diagram of a NOR-structure flash memory in the prior art. Such as figure 1 As shown, the two NOR-structure flash memory units 10a and 10b in the NOR...

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Problems solved by technology

The electrical isolation between the drain electrode 150 and the gate electrode is mainly realized by the dielectric layer 160 and / or the ILD barrier layer 140 (thicknesses of the dielectric layer 160 and the ILD barrier layer 140 may be exaggerated in the figure), and the voltage between the two When the difference is large, the voltage difference between the gate electrode and the drain electrode 150 is likely to cause figure 1 Leakage current shown

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