A buffer layer structure of igbt and its manufacturing method
A manufacturing method and technology of a buffer layer, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve the problems of inaccurate doping concentration distribution control of the buffer layer, slow switching speed, etc., to improve switching speed, reduce Small conduction voltage drop, the effect of reducing chip thickness
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Embodiment 1
[0028] see image 3 , The embodiment of the present invention provides a buffer layer structure of an IGBT, the structure of the IGBT includes a front MOS structure, an N-drift region, a buffer layer, a P+ collector region on the back and a collector on the back. The front MOS structure is located on one side of the N-drift region, including a P-type base region 5, an N+ emitter region 6, a gate oxide layer 8, a gate 7, and an emitter 9. The buffer layer is connected to the N-drift region 4 and is located at the The opposite side of the front MOS structure; the P+ collector area 1 on the back is connected to the buffer layer, and the collector 10 is connected to the P+ collector area 1 on the back, that is, the P+ collector area 1 is located between the buffer layer and the collector 10; the buffer The doping type of the layer is N-type, the N+ buffer layer includes a multi-layer N-type doped layer, the multi-layer N-type doped layer includes at least two N-type doped layers, ...
Embodiment 2
[0030] The embodiment of the present invention also provides a method for fabricating a buffer layer structure of an IGBT, comprising the following steps:
[0031] Step 201: Select a substrate, the substrate is a single crystal material, and the substrate includes an N-drift region; then fabricate a MOS structure on the surface of one side of the substrate to form the gate structure and source structure of the device; MOS The structure can be a groove structure or a planar structure, and the preparation of the MOS structure can be realized by conventional techniques; in the embodiment of the present invention, the MOS structure is a planar structure, specifically:
[0032] Step 2011: Passing a high-temperature gas containing a certain proportion of oxygen into the furnace tube to form a silicon oxide film on the silicon surface;
[0033] Step 2012: Uniformly cover a layer of photoresist on the surface of the silicon, and use a terminal ring mask to expose the ring area. Then ...
Embodiment 3
[0048] The embodiment of the present invention also provides a method for fabricating a buffer layer structure of an IGBT, comprising the following steps:
[0049] Step 301: select a substrate, the substrate is a single crystal material, and the substrate includes an N-type drift region; then fabricate a MOS structure on the surface of one side of the substrate to form a gate structure and a source structure of the device; The MOS structure can be a trench structure or a planar structure, and the preparation of the MOS structure can be realized by conventional techniques; in the embodiment of the present invention, the MOS structure is a planar structure, and the specific manufacturing method can be referred to in Embodiment 1. Steps 2011-2017;
[0050] Step 302: On the side opposite to the MOS structure, grind the N-type substrate to a desired thickness. Devices of different voltage levels correspond to different thicknesses of the drift region after thinning. Generally spea...
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