One-time molding method of tsv, m1, ct metal layers based on the method of making through-holes

Abstract

The invention discloses a TSV, M1 and CT metal layer one-time forming method based on a via middle manufacturing method. The method comprises the step of carrying out photoetching and etching on TSV, removing the TSV photoresist and carrying out cleaning, the step of depositing an oxidation layer of a contact hole CT after surface planarization processing, the step of depositing oxide of a TSV insulating layer, the step of carrying out primary BARC filling and etching, the step of carrying out CT photoetching and etching on the contact hole, the step of removing the CT photoresist of the contact hole and carrying out cleaning, the step of carrying out secondary BARC filling and etching, the step of carrying out photoetching and etching on a metal wire layer M1, the step of depositing a diffusion blocking layer and a seed layer, the step of metal electric conduction article filling, and the step of carrying out the surface planarization process. Synchronous finishing of the diffusion blocking layer, the seed layer and the metal filling article and one-time planarization processing in the process of manufacturing the contact hole CT, the silicon through hole TSV and the metal wire layer can be achieved at the same time, the material utilizing ratio is improved, production cost is reduced, and production efficiency is improved.

Description

technical field [0001] The invention relates to the technical field of microelectronics, in particular to a process method for one-time forming of TSV, M1 and CT metal layers in an integrated circuit. Background technique [0002] With the development of integrated circuit technology, in addition to the high-speed, low power consumption, and high reliability performance requirements for the device itself, the development of interconnection technology is also affecting the overall performance of the device to an increasing extent. Reducing the RC delay time (where R is the resistance of the interconnect metal and C is the dielectric-dependent capacitance) to a level comparable to the device delay is a big challenge. The through-silicon via technology (TSV technology for short) can effectively reduce the RC delay. TSV technology realizes the interconnection of chips through the vertical conduction between chips and wafers, so it has become an advanced The core of the three-di...

AI Technical Summary

Problems solved by technology

[0007] Usually, the viamiddle method of MOS devices is used to make the TSV and the metal line layer M1. After the contact hole CT is etched, filled, and mechanically polished, the through-silicon via TSV and the metal line need to be completed separately. Layer M1 process has the disadvantages of long production cycle, cumbersome process steps and high cost

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