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Method for manufacturing semiconductor device

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problems of long production cycle, cumbersome process, shortening process flow and production cycle, etc.

Inactive Publication Date: 2014-09-03
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The present invention provides a method for manufacturing a semiconductor device to solve the problems of cumbersome process and long production cycle in the prior art, shorten the process flow and production cycle, and achieve the purpose of reducing production cost

Method used

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  • Method for manufacturing semiconductor device
  • Method for manufacturing semiconductor device
  • Method for manufacturing semiconductor device

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Experimental program
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Embodiment 1

[0046] figure 1 It is a flow chart of the manufacturing method of the semiconductor device of the present embodiment, Figure 2 to Figure 11 It is a schematic cross-sectional view of the device in the manufacturing method of the semiconductor device in this embodiment. Combine below Figure 1 to Figure 11 Describe in detail the semiconductor device manufacturing method using stress memory technology of the present invention, the manufacturing method includes the following steps:

[0047] Step S111: providing a substrate 100;

[0048] like figure 2As shown, the material of the substrate 100 can be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon-germanium compound or silicon-on-insulator (SOI), etc., and the substrate 100 is usually formed with a shallow trench isolation structure (STI ) 200. In this embodiment, the substrate 100 includes an NMOSFET region 101 , a PMOSFET region 102 , a high resistance region 103 and a non-high resistance region...

Embodiment 2

[0067] The difference between this embodiment and Embodiment 1 is that the stress layer on the non-high resistance region is removed in the second photolithography.

[0068] Combine below Figure 12 to Figure 17 The semiconductor device manufacturing method using the stress memory technology of this embodiment is described in detail, the manufacturing method includes the following steps:

[0069] Step S111: providing a substrate 100;

[0070] like Figure 12 As shown, the substrate 100 includes an NMOSFET region 101 , a PMOSFET region 102 , a high resistance region 103 and a non-high resistance region 104 .

[0071] Step S112: forming a stress layer 105 on the substrate 100;

[0072] like Figure 13 As shown, a silicon oxide layer 1051 and a silicon nitride layer 1052 are sequentially formed on the substrate 100 .

[0073] Step S113: performing photolithography on the stress layer 105 for the first time;

[0074] like Figure 14 As shown, a first photoresist 106 is form...

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Abstract

The invention discloses a method for manufacturing a semiconductor device, and the method includes: providing a substrate which includes an NMOSFET area, a PMOSFET area, a non-high resistance area and a high resistance area; forming a stress layer on the substrate; performing primary photoetching on the stress layer, and removing the stress layer on the PMOSFET area; performing annealing treatment on the stress layer; performing secondary photoetching on the stress layer, removing the stress layer on the NMOSFET area, and keeping the stress layer on the high resistance area. By adoption of the abovementioned method for manufacturing the semiconductor device, a deposition process and an etching process of forming a self-aligned metal silicide barrier layer on the high resistance area are omitted, process steps are reduced, a production cycle is shortened, and thus production cost is reduced.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a method for manufacturing semiconductor devices using stress memory technology (SMT). Background technique [0002] Applying stress is an effective way to improve the carrier mobility of metal-oxide-semiconductor field-effect transistors (MOSFETs) and reduce the series resistance of MOSFETs. Only relatively minor modifications to the semiconductor process are required to effectively improve the performance of MOSFETs. [0003] When stress is applied to the channel of a semiconductor transistor, both the mobility of carriers and the conduction current of the transistor change. This is because the applied stress and resulting strain on the semiconductor structure within the channel affects the bandgap structure and can change the effective mass of carriers. The effect of this stress depends on the crystallographic orientation of the channel facet, the direction of ...

Claims

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Application Information

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IPC IPC(8): H01L21/8238
CPCH01L21/8238
Inventor 刘达沈旭昭刘磊
Owner SEMICON MFG INT (SHANGHAI) CORP
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