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Low-input capacitance power semiconductor field effect transistor and self-alignment manufacture method thereof

A technology of field effect transistors and power semiconductors, applied in semiconductor/solid-state device manufacturing, semiconductor devices, circuits, etc., can solve the problems of device switching speed reduction, increase switching power loss, and reduce circuit efficiency, so as to reduce input capacitance and improve Effect of switching speed and shortening switching time

Inactive Publication Date: 2015-03-04
JILIN SINO MICROELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In order to solve the problem that the Miller capacitive effect occurs in the MOSFET device structure in the prior art, the switching speed of the device is reduced, the switching power loss is increased, and the circuit efficiency is reduced, the present invention provides a low input capacitance power semiconductor field effect transistor and its self-alignment method

Method used

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  • Low-input capacitance power semiconductor field effect transistor and self-alignment manufacture method thereof
  • Low-input capacitance power semiconductor field effect transistor and self-alignment manufacture method thereof
  • Low-input capacitance power semiconductor field effect transistor and self-alignment manufacture method thereof

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Embodiment approach 1

[0026] Take the VDMOSFET device as an example, such as figure 2 As shown, the polysilicon gate of the existing device is disconnected at the edge of the JFET region, and is divided into the polysilicon gate of the device and the polysilicon field plate of the active region, forming a image 3 In the low input capacitance power semiconductor field effect transistor shown, the width of the polysilicon gate is less than or equal to the channel length, and the distance between the polysilicon gate and the polysilicon field plate is between 0.2 microns and 5 microns, and the distance is greater than 4 times the thickness of the gate oxide layer above. As shown in FIG. 4 , the polysilicon field plate is connected to the metal in the source region of the device at the edge of the active region of the chip to form a capacitance between DSs of the device.

[0027] Such as Figure 5 Shown, the equivalent circuit of a conventional VDMOSFET device. In the low input capacitance power s...

Embodiment approach 2

[0034] Figure 7 It is a cross-sectional view of a VDMOSFET chip according to an implementation of the present invention. The polysilicon gate of the device is disconnected at the edge of the JFET region, and is divided into the polysilicon gate of the device and the polysilicon field plate on the JFET region to realize the automatic separation of the polysilicon gate and the polysilicon field plate. aligned, formed as Figure 7 The structure, wherein the width of the polysilicon gate is less than or equal to the channel length, and the distance between the polysilicon gate and the polysilicon field plate is between 0.2 microns and 5 microns, and is more than 4 times greater than the thickness of the gate oxide layer. The tops of the polysilicon gates on both sides are connected through a polysilicon layer, and the structure is separated from the polysilicon field plate through an insulating layer.

[0035] The polysilicon field plate is connected to the source metal of the d...

Embodiment approach 3

[0044] Such as Figure 8 As shown, it is the improvement made in the second embodiment. In order to better reduce the device off-voltage stress, increase the thickness of the gate oxide layer, reduce the Cgs capacitance, reduce the thickness of the insulating layer under the polysilicon field plate, and increase the Cds' capacitance. To increase the turn-off speed, increase the Cds capacitor to absorb the voltage stress generated during the turn-off process. Realize zero voltage turn off.

[0045] The process implementation method includes the following steps:

[0046] Step 1, thermal oxidation is performed on the epitaxial layer to form a gate oxide layer, and the thickness of the oxide layer is

[0047] Step 2: Etch the oxide layer under part of the polysilicon field plate by photolithography, leaving the remaining oxide thickness The etch width is slightly wider than the width of the polysilicon field plate.

[0048] Step 3: Deposit a layer of polysilicon with a th...

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Abstract

The invention relates to a low-input capacitance power semiconductor field effect transistor and a self-alignment manufacture method thereof and belongs to the semiconductor device technical field. The objective of the invention is to solve the problem of a Miller capacitance effect in an existing MOSFET device structure. A polysilicon gate of the semiconductor field effect device is disconnected at edges of two sides of a JFET region, so that polysilicon gates at two sides and a polysilicon field plate on the JFET region at the middle can be formed; an interval is formed between the polysilicon gates at two sides and the polysilicon field plate respectively; and the polysilicon field plate is connected with source region metal of the device at the edge of an active region of a chip, so that a capacitor between the DS of the device can be formed. The method includes the following steps that: a gate oxide layer is grown on an epitaxial layer, and a polysilicon layer is deposited on the gate oxide layer, and photo etching is performed, and therefore, polysilicon gates and a polysilicon field plate can be formed; an insulating layer is deposited; photo etching is performed on the insulating layer so as to expose the polysilicon gates at two sides; and injection and diffusion of a P well region and an N+ source region are performed, and photo etching is performed on contact holes of the gates and sources, and front-surface and back-surface metallization treatment is performed.

Description

technical field [0001] The invention relates to metal oxide semiconductor field effect transistors, especially power semiconductor devices such as power VDMOSFET, IGBT, planar (channel parallel chip surface) superstructure DMOS and IGBT, and in particular to low input capacitance power semiconductor field effect transistors and The self-alignment manufacturing method belongs to the technical field of semiconductor devices. Background technique [0002] Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are widely used as switching devices in fields such as power supplies. Such as figure 1 As shown, the basic principle of metal-oxide-semiconductor field-effect transistors is to form a semiconductor surface in NPN, on the P-type region and cover the PN junctions on both sides, and form an oxide layer metal (or silicon) gate structure on it, using the gate below The P-type region forms an inversion layer under the gate bias to connect the N-type regions on both side...

Claims

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Application Information

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IPC IPC(8): H01L29/40H01L29/78H01L21/336
CPCH01L29/402H01L29/66712H01L29/7802
Inventor 左义忠高宏伟张海宇贾国
Owner JILIN SINO MICROELECTRONICS CO LTD
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