Low subthreshold oscillation range and high voltage withstanding insulated gate tunneling transistor and preparing method thereof

Abstract

The invention relates to a low subthreshold oscillation range and high voltage withstanding insulated gate tunneling transistor. The forward and reverse voltage withstanding capability of the device is improved by introducing a low impurity concentration of voltage withstanding layer structure into a collector junction and an emitter junction, and lower subthreshold oscillation range and better switching On-Off properties are realized through the utilization of the extremely sensitive correlation between the resistance of a tunneling insulating layer and electric field intensity in the tunneling insulating layer. Tunneling current generated on the insulated tunneling layer is used as the driving current of a collector electrode, and better forward current conducting properties are realized in contrast with a common semiconductor band gap tunneling field effect transistor. The invention further provides a specific making method of the low subthreshold oscillation range and high voltage withstanding insulated gate tunneling transistor. Therefore, the work properties of a nanoscale integrated circuit unit are obviously improved, and the transistor is suitable for being popularized and applied.

Description

Technical field: [0001] The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to a low subthreshold swing, high withstand voltage insulating gate tunneling transistor and a manufacturing method thereof, which are suitable for manufacturing high-performance ultra-high integrated integrated circuits. Background technique: [0002] At present, the continuous shortening of the channel length of integrated circuit unit metal oxide semiconductor field effect transistors (MOSFETs) has led to the increase of the subthreshold swing of the device, which has brought about serious degradation of switching characteristics and a significant increase in static power consumption, etc. short channel effect. Although the degradation of the device performance can be alleviated by improving the gate electrode structure, when the device size is further reduced to below 50 nm, even with the optimized gate electrode structure, the subthreshold swing ...

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Problems solved by technology

However, this approach not only increases the production cost, but also increases the difficulty of the process.

In addition, the use of high dielectric constant insulating materials as the insulating dielectric layer between the gate and the substrate can only improve the control ability of the gate to the electric field distribution of the channel, but cannot essentially increase the tunneling probability of silicon materials, so The improvement of electrical characteristics such as sub-threshold slope conduction current is very limited

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