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Method for preparing sapphire pattern substrate

A sapphire substrate, pattern substrate technology, applied in electrical components, circuits, semiconductor devices, etc., can solve the problems of difficulty, small size of single crystal, high dissociation pressure, etc., to achieve smooth and flat surface without defects, improved crystal quality, The effect of low process cost

Inactive Publication Date: 2015-04-01
XIAN SHENGUANG ANRUI PHOTOELECTRIC TECH
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  • Application Information

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Problems solved by technology

It is difficult to directly synthesize GaN single crystal. Due to the high dissociation pressure of nitrogen, high temperature and high pressure conditions are required, and the size of the grown single crystal is small, which cannot meet the production requirements. Therefore, commercial GaN-based devices basically use heterogeneous Epitaxy
However, due to the large lattice mismatch and thermal expansion mismatch coefficient between the heterogeneous substrate material and GaN, it is easy to cause large stress and high dislocation density during epitaxial growth, which will reduce carrier mobility and lifetime. and material thermal conductivity, while dislocations will form non-radiative recombination centers and light scattering centers, resulting in a decrease in the luminous efficiency of optoelectronic devices

Method used

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Embodiment Construction

[0026] Such as figure 2 Shown, the present invention grows patterned sapphire substrate, mainly comprises the following steps:

[0027] 1) Deposit a layer of 100-300nm SiO on a sapphire substrate by PECVD 2 layer, the deposition temperature is 200-300°C.

[0028] 2) On SiO 2 A layer of 8-15nm thick Ni film is vapor-deposited on it, and Ni nano-islands are formed by rapid thermal annealing under a nitrogen atmosphere. The annealing temperature is 700-1000° C. for 1-3 minutes. The Ni nano-islands have an average diameter of 100-200 nm and a density of 3-5×10 8 / cm 2 .

[0029] 3) Using Ni nano-islands as a mask, use reactive ion etching (RIE) to etch SiO 2 layer, the etchant gas is CF 4 or CHF 3 and SF 6 , the etching rate is controlled at 50-66nm / min, and the etching time is 1-6min. SiO is obtained after etching 2 nanopillars.

[0030] 4) HNO at 50-150°C 3 Soak in the solution for 5-10min to remove the Ni film.

[0031] Specific examples are as follows:

[0032]...

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Abstract

The invention provides a method for preparing a sapphire pattern substrate, so as to further improve the crystal quality of a heteroepitaxial growth structure and improve the lighting effect. The method mainly comprises the following steps: 1) preparing a layer of SiO2 film on a sapphire substrate; 2) further carrying out thermal evaporation on the SiO2 film to form a layer of Ni film, and preparing an Ni nano island through a rapid thermal annealing method; 3) with the Ni nano island as a mask, etching the SiO2 layer by virtue of a reaction ion etching method (RIE) or a hydrofluoric acid solution, so as to obtain an SiO2 nano pillar array; 4) removing the Ni layer, so as to obtain the sapphire pattern substrate with the SiO2 nano pillar array.

Description

Technical field: [0001] The invention belongs to the technical field of LED patterned substrates, and mainly relates to a preparation method of a sapphire patterned substrate. Background technique: [0002] Gallium nitride (GaN) semiconductor material has excellent characteristics such as high luminous efficiency, high thermal conductivity, high temperature resistance, radiation resistance, acid and alkali resistance, high strength and high hardness. It is difficult to directly synthesize GaN single crystal. Due to the high dissociation pressure of nitrogen, high temperature and high pressure conditions are required, and the size of the grown single crystal is small, which cannot meet the production requirements. Therefore, commercial GaN-based devices basically use heterogeneous epitaxy. However, due to the large lattice mismatch and thermal expansion mismatch coefficient between the heterogeneous substrate material and GaN, it is easy to cause large stress and high disloc...

Claims

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Application Information

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IPC IPC(8): H01L33/22H01L33/00
CPCH01L33/22H01L33/007
Inventor 韩沈丹黄宏嘉
Owner XIAN SHENGUANG ANRUI PHOTOELECTRIC TECH
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