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Thicker bottom oxide for reduced Miller capacitance in trench metal oxide semiconductor field effect transistor (MOSFET)

一种半导体、氧化物的技术,应用在制备沟槽半导体功率器件领域,能够解决减薄、IPO厚度不均匀、多晶硅过度回刻等问题

Inactive Publication Date: 2015-08-05
ALPHA & OMEGA SEMICON INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The downside of this approach is that it is difficult to control the thickness of the IPO on the wafer
The thickness of the IPO depends on two independent, unrelated etch-back steps, resulting in under-etch-back of polysilicon or over-etch-back of polysilicon or both, resulting in non-uniform and localized thinning of the IPO

Method used

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  • Thicker bottom oxide for reduced Miller capacitance in trench metal oxide semiconductor field effect transistor (MOSFET)
  • Thicker bottom oxide for reduced Miller capacitance in trench metal oxide semiconductor field effect transistor (MOSFET)
  • Thicker bottom oxide for reduced Miller capacitance in trench metal oxide semiconductor field effect transistor (MOSFET)

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Embodiment Construction

[0050] In an embodiment of the invention, a separate processing step is used to make the thickness of the bottom dielectric layer greater than the thickness of the dielectric layer on the sidewalls of the trench, as described below. A thicker bottom dielectric layer reduces the capacitance between the trench gate and the drain of the DMOS transistor.

[0051] Figures 3A to 3O represents an embodiment in accordance with the present invention with a variable thickness gate trench oxide for Figure 1D Cross-sectional view of the fabrication process for trench DMOS with isolated polysilicon gates of the type shown.

[0052] Such as Figure 3A As shown, a trench 306 with a width A is formed in the semiconductor substrate 302 . By way of example, and not limitation, trenches 306 may be utilized with a hard mask (not expressly shown), such as an oxide or nitride hard mask, and then removed or left in place. Optionally, trenches 306 are formed using a photoresist (PR) film (not s...

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Abstract

Semiconductor device fabrication method and devices are disclosed. The semiconductor power device is formed on a semiconductor substrate having a plurality of trench transistor cells each having a trench gate. Each of the trench gates having a thicker bottom oxide (TBO) formed by a REOX process on a polysilicon layer deposited on a bottom surface of the trenches.

Description

technical field [0001] The present invention mainly relates to the method and structure of preparing trench semiconductor power devices (such as DMOS devices), more precisely, the present invention relates to the preparation of device structures and structures of trench semiconductor power devices with variable-thickness gate oxides. method. Background technique [0002] A DMOS (Double Diffused MOS) transistor is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that utilizes two successive diffusion steps aligned to a common edge, forming the channel region of the transistor. DMOS transistors are commonly used as high-voltage, high-current devices, as stand-alone transistors, or as components in power integrated circuits. The advantage of this application is that DMOS transistors can provide high current per unit area with very low forward voltage drop. [0003] A typical DMOS transistor is a trench DMOS transistor. In this type of DMOS transistor, the gate is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/423H01L21/336H01L21/28
CPCH01L29/4916H01L29/66734H01L21/02164H01L21/0332H01L21/28035H01L21/3212H01L21/31111H01L21/0217H01L29/7813H01L29/51H01L21/02238H01L29/4236H01L29/407H01L29/42368H01L29/66719H01L21/31144H01L29/518
Inventor 李亦衡王晓彬
Owner ALPHA & OMEGA SEMICON INC