Thicker bottom oxide for reduced Miller capacitance in trench metal oxide semiconductor field effect transistor (MOSFET)
一种半导体、氧化物的技术,应用在制备沟槽半导体功率器件领域,能够解决减薄、IPO厚度不均匀、多晶硅过度回刻等问题
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[0050] In an embodiment of the invention, a separate processing step is used to make the thickness of the bottom dielectric layer greater than the thickness of the dielectric layer on the sidewalls of the trench, as described below. A thicker bottom dielectric layer reduces the capacitance between the trench gate and the drain of the DMOS transistor.
[0051] Figures 3A to 3O represents an embodiment in accordance with the present invention with a variable thickness gate trench oxide for Figure 1D Cross-sectional view of the fabrication process for trench DMOS with isolated polysilicon gates of the type shown.
[0052] Such as Figure 3A As shown, a trench 306 with a width A is formed in the semiconductor substrate 302 . By way of example, and not limitation, trenches 306 may be utilized with a hard mask (not expressly shown), such as an oxide or nitride hard mask, and then removed or left in place. Optionally, trenches 306 are formed using a photoresist (PR) film (not s...
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