An electrostatic discharge protection device with low trigger voltage

Abstract

An electrostatic discharge protection device with low trigger voltage comprises a P-type substrate, wherein a P-type epitaxial layer is arranged on the P-type substrate, an N-type drift region is arranged on the P-type epitaxial layer, an N-type drain region, a shallow slot isolation region and a first field oxide layer are arranged in the N-type drift region, a gate oxide layer, an N-type source region and a P-type body region are further arranged on the P-type epitaxial layer, a poly-silicon gate is arranged on the gate oxide layer, and a drain metal contact, a gate metal contact, a source metal contact and a body region metal contact are respectively arranged on the upper surfaces of the N-type drain region, the poly-silicon gate, the N-type source region and the P-type body region and pass through a passivation layer. The electrostatic discharge protection device is characterized in that isolation means comprising deep slot isolation regions and sheet-shaped field oxide layers are arranged between the N-type source region and the P-type body region, and the deep slot isolation regions and the sheet-shaped field oxide layers are arranged at intervals. By the electrostatic discharge protection device, the trigger voltage of the device can be reduced, the secondary breakdown current is increased, and the robustness of the device during the electrostatic discharge (ESD) process is improved.

Description

technical field [0001] The invention relates to the reliability field of integrated circuits, and relates to an electrostatic discharge protection device structure with low trigger voltage. Background technique [0002] With the improvement of integration and the reduction of device feature size, how to ensure the reliability of devices has become more and more important. According to statistics, electrical overstress (EOS) and electrostatic discharge (ESD) damage account for about 40% of the failure factors of related semiconductor integrated circuits. The reason is that the high electric field or instantaneous high current caused by electrostatic discharge and electrical overstress will cause local overheating of the device, causing breakdown of the dielectric layer, burning of polysilicon or metal wiring, destruction of the passivation layer, and secondary heat generation of the PN junction and even the device. Breakdown, even melting the silicon die and other issues. T...

AI Technical Summary

Problems solved by technology

However, high-voltage LDMOS devices exhibit larger snapbacks than low-voltage MOS devices, and the sustain voltage of LDMOS devices is much lower than the trigger voltage.

Although the trigger voltage can be reduced by auxiliary triggering methods such as gate coupling and substrate triggering, there are problems of increasing the complexity of the circuit design and increasing the layout area.

Therefore, under normal circumstances, the multi-finger uniform trigger condition where the failure voltage is greater than the trigger voltage cannot be satisfied, making it more difficult to trigger uniformly than low-voltage multi-finger devices, and there is a serious multi-finger non-uniform turn-on problem that directly affects the on-chip ESD protection capability of high-voltage circuits.

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