HVMOS integrated with demagnetization sampling device, and demagnetization sampling circuit

Abstract

The invention provides an HVMOS (high-voltage metal oxide semiconductor) integrated with a demagnetization sampling device, comprising a P substrate, an N drift region, an N-type doping drain end, a field oxide layer, a gate oxide layer, a P-type well source end, a field plate and a gate. The field plate and the drain end form a high-voltage covered capacitor through a medium therebetween. The independent high-voltage covered capacitor put forward in the invention is integrated in the HVMOS device without increasing the area of the HVMOS device. Moreover, the size of the high-voltage covered capacitor is adjustable, the use of the high-voltage capacitor is not influenced by series connection between a gate-source capacitor and a gate-substrate capacitor, the high-voltage capacitor is not connected in parallel with a traditional high-voltage drain-gate capacitor and is not affected by the Miller effect between the drain and the gate, and the high-voltage covered capacitor can be used as a demagnetization sampling device. The HVMOS area and the chip area are reduced.

Description

technical field [0001] The invention relates to the field of integrated circuit design, in particular to an HVMOS integrated demagnetization sampling device. Background technique [0002] In the design of the LED drive circuit, how to detect the end signal of the inductance demagnetization of the peripheral system in order to realize the constant current output of the system has become one of the keys to the current LED drive design. The method of sampling the demagnetization signal to the chip can be divided into two categories: 1. Use the resistor divider network around the chip to sample the demagnetization signal of the inductor and the primary coil of the transformer to the chip feedback port. 2. Use the demagnetization signal of the internal capacitor sampling system of the chip. The disadvantages of the first type of sampling technology are: (1), auxiliary windings and voltage divider resistors are required around the system, which increases the system cost; (2), the...

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Problems solved by technology

The disadvantages of the first type of sampling technology are: (1), the peripheral of the system needs auxiliary windings and voltage divider resistors, which increases the system cost; (2), the chip demagnetization signal feedback port is susceptible to interference

The second type of sampling often uses high-voltage gate-to-drain parasitic capacitance of switching devices for sampling. The disadvantages are: (1) The high-voltage drain-gate parasitic capacitance of switching devices has a relatively small capacitance value, and depletion capacitance will be introduced due to the increase in drain voltage , so that the drain-gate parasitic capacitance is connected in series with the depletion capacitance, so that the equivalent drain-gate capacitance decreases

In order to increase the capacitance value, it is necessary to increase the area of ​​the high-voltage switching device, which seriously wastes the chip area; (2), the gate-drain capacitance forms a series relationship with the gate-source capacitance and the gate-substrate capacitance at the same time. In actual use, the gate-drain capacitance The capacitor is affected and cannot be used as an independent high-voltage capacitor

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