A kind of semiconductor device and its manufacturing method, electronic device

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof, and an electronic device. The method comprises steps: S1, a semiconductor substrate is provided, a doped oxide layer is formed on the semiconductor substrate, and a plurality of virtual cores arranged at intervals are formed on the doped oxide layer; S2, a gap wall material layer is deposited to cover the virtual cores and the semiconductor substrate; S3, CF3I and H2 are selected to etch the gap wall material layer to form a gap wall on the side wall of the virtual core; and S4, the virtual core is removed to obtain a fin pattern. The method of the invention has the advantages that the dual-pattern manufacturing method is more robust, and a manufactured FinFET has better performance and yield.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, in particular, the present invention relates to a semiconductor device, a manufacturing method thereof, and an electronic device. Background technique [0002] The improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. Currently, as the semiconductor industry in pursuit of high device density, high performance, and low cost has evolved to smaller technology process nodes, manufacturing and design challenges have promoted the development of three-dimensional designs such as Fin Field Effect Transistors (FinFETs). [0003] Compared with the existing planar transistors, FinFET devices have more superior performance in terms of channel control and reducing shallow channel effects; wherein, the planar gate structure is arranged above the channel, and in the FinFET the gate Arranged arou...

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Problems solved by technology

[0007] Among them, the spacer is widely used in self-aligned double patterning (Self-aligned double patterning, SADP), usually using lithography-etch-film deposition-etch-removal-nucleus-etch (Litho–Etch–film deposition-Etch –Strip–Etch.) method to prepare a semiconductor device, for example, select amorphous carbon A-C and pattern it as the core (core) in the double pattern, then select a low-temperature deposition method to form a spacer layer on the A-C, and finally remove all A-C core, the method usually forms a cone-shaped core and also causes a burden when the dielectric anti-reflective coating (dielectricAnti-reflective coating, DRAC) is covered. In addition, there are odd-even (Even-odd) problems, such as odd- Even-numbered critical dimensions are not uniform enough (Even-odd CD loading). In the prior art, polysilicon is usually selected to replace the A-C to prepare polysilicon cores, but polysilicon is easily oxidized during the preparation process, which will also cause even-odd (Even-odd CD loading). ) problem, so that the critical dimensions of the final fins are not uniform enough

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