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Semiconductor device and preparation method thereof and electric device

A technology of electronic devices and semiconductors, which is applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, electric solid-state devices, etc., and can solve problems such as serious masking effects of photoresist layers

Active Publication Date: 2017-04-26
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Threshold voltage ion implantation is usually required to adjust the threshold voltage of SRAM during the preparation of SRAM devices, but for the threshold voltage ion implantation of the pull-down transistor of the SRAM, the shadowing effect of the photoresist layer is very serious, because the shadowing effect passes through It is not possible to adjust the threshold voltage of NMOS pull-down transistors by ion implantation

Method used

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  • Semiconductor device and preparation method thereof and electric device
  • Semiconductor device and preparation method thereof and electric device
  • Semiconductor device and preparation method thereof and electric device

Examples

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Embodiment 1

[0041] The semiconductor device and the preparation method of the present invention will be further described below in conjunction with the accompanying drawings, wherein, Figures 1a-1k It is a schematic diagram of the preparation process of the semiconductor device described in the present invention; figure 2 It is a process flow chart for preparing the semiconductor device of the present invention.

[0042] Step 101 is executed to provide a semiconductor substrate 101 and perform ion implantation to form a well.

[0043]In this step, the semiconductor substrate 101 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S- SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

[0044] Wherein the semiconductor substrate 101 includes a logic area and an active area, wherein an SRAM device can be formed in the active area, and the active area fu...

Embodiment 2

[0096] The present invention also provides a semiconductor device, and the present invention also provides a semiconductor device, and the semiconductor device is prepared by the method described in Embodiment 1.

[0097] The semiconductor device includes:

[0098] A semiconductor substrate 101, the semiconductor substrate includes a logic region and an active region, wherein the active region includes NMOS and PMOS to serve as a pull-down transistor and a pull-up transistor respectively, and the PMOS is formed in the logic region to serve as logic region pull-down transistor;

[0099] The fin 102 is located on the semiconductor substrate, and the fin has a stepped structure, wherein the stepped structure;

[0100] an isolation material layer 106 located on the semiconductor substrate and covering part of the fins;

[0101] Wherein, in the pull-up transistor, a phosphorus-containing material layer 105 is formed on the surface of the fins of the stepped structure, wherein a p...

Embodiment 3

[0109] The present invention also provides an electronic device, including the semiconductor device described in the second embodiment. Wherein, the semiconductor device is the semiconductor device described in the second embodiment, or the semiconductor device obtained according to the preparation method described in the first embodiment.

[0110] The electronic device of this embodiment can be any electronic product or equipment such as mobile phone, tablet computer, notebook computer, netbook, game console, TV set, VCD, DVD, navigator, camera, video recorder, voice recorder, MP3, MP4, PSP, etc. , can also be any intermediate product including the semiconductor device. The electronic device according to the embodiment of the present invention has better performance due to the use of the above-mentioned semiconductor device.

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PUM

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Abstract

The invention relates to a semiconductor device and a preparation method thereof and an electric device. The method comprises the following steps: S1) providing a semiconductor substrate, and forming fins, in a first height, of a logic area pull-down transistor, an active region pull-up transistor and an active region pull-down transistor on the semiconductor substrate; S2) forming a substrate oxide layer on the fins and the semiconductor substrate and forming gap walls on liner oxide layers on the side walls of the fins; S3) with the gap walls being masks, etching the semiconductor substrate to form step-type fins in a second height; S4) removing the gap walls and forming a phosphorus containing material layer on the surfaces of the fins of the active region pull-up transistor to cover the surfaces of the fins and the gap walls; and S5) depositing an isolation material layer, and meanwhile, carrying out annealing to enable the phosphorus in the phosphorus containing material layer to be diffused so as to adjust the threshold voltage. The method improves device performance and qualified rate.

Description

technical field [0001] The present invention relates to the field of semiconductors, in particular, the present invention relates to a semiconductor device, a preparation method thereof, and an electronic device. Background technique [0002] With the continuous development of semiconductor technology, the improvement of integrated circuit performance is mainly achieved by continuously shrinking the size of integrated circuit devices to increase its speed. At present, due to the demand for high device density, high performance, and low cost, the semiconductor industry has advanced to the nanotechnology process node, and the fabrication of semiconductor devices is limited by various physical limits. [0003] As the size of CMOS devices continues to shrink, the short-channel effect has become a key factor affecting device performance. Compared with existing planar transistors, FinFETs are advanced semiconductor devices used for 20nm and below process nodes, which can effective...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8244H01L27/11H01L21/8238H10B10/00
CPCH01L21/823821H10B10/12
Inventor 周飞
Owner SEMICON MFG INT (SHANGHAI) CORP