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High-speed clock data recovery circuit of novel structure

A high-speed clock, new structure technology, applied in the direction of electrical components, power automatic control, etc., can solve the problems of large area consumption, difficult design of linear phase detectors, etc., to save area and power consumption, solve the core voltage reduction, and improve the The effect of process portability and flexibility

Inactive Publication Date: 2017-05-10
北京华大九天科技股份有限公司
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Problems solved by technology

The disadvantage of this structure is that the feedback loop is done by analog technology, the linear phase detector becomes difficult to design as the speed increases, and the analog loop filter containing the capacitor is unavoidable, and the capacitor is in the chip. Realization requires a large amount of area

Method used

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  • High-speed clock data recovery circuit of novel structure
  • High-speed clock data recovery circuit of novel structure
  • High-speed clock data recovery circuit of novel structure

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Embodiment Construction

[0021] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0022] Such as image 3 As shown, after the high-speed serial data is shaped by the input data buffer, it enters the high-speed phase detector. The high-speed clocks CKI and CKQ with a difference of 90 degrees sample the serial data on both edges. The phase relationship between the high-speed clock and the serial data is obtained by XOR processing. The UP and DWN control signals output by the phase detector enter the digital loop filter for filtering processing, and the processed UP1 and DWN1 drive the phase interpolation controller to generate corresponding control information to drive the phase interpolator, and the high-speed clock output by the phase interpolator enters the detector phase device, thereby forming a negative feedback closed-loop system, and finally the phase relationship between the high-speed clock and data is locked at ...

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Abstract

The invention relates to a high-speed clock data recovery circuit of a novel structure. The high-speed clock data recovery circuit is composed of such modules as a high-speed digital phase discriminator, a digital loop filter, a phase interpolation controller, a phase interpolator and the like. By use of such a digital interpolation based clock data recovery circuit, the problems of increased design difficulty and poor reliability caused by core voltage reduction of a deep submicron CMOS process are solved, and the circuit also has quite good process transplantability and flexibility. Since most of the circuit is realized in a digital domain, compared to a conventional simulation structure, the area and the power consumption are effectively saved. The circuit is completely compatible with a standard deep submicron CMOS process, the manufacturing cost can be reduced, and promotion and application are facilitated.

Description

technical field [0001] The invention of a high-speed clock data recovery circuit with a new structure belongs to the technical field of integrated circuits, in particular the circuit structure design and method for high-speed serial data receiving end clock data recovery. Background technique [0002] With the development of electronic industry technology, especially in the development of transmission interface, the data bandwidth is getting higher and higher, the speed of traditional parallel interface can no longer meet the demand, replaced by faster serial interface, serial data communication can Save connection resources, have small requirements for signal amplitude, and small crosstalk between signals, high transmission speed, widely used in various communication and consumer serial standards such as Ethernet, hard disk data transmission, high-definition image transmission, etc. . [0003] In the serial communication system, the clock data recovery circuit plays a key ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/107
CPCH03L7/1077H03L2207/50
Inventor 唐重林刘寅刘伟平
Owner 北京华大九天科技股份有限公司
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