Gate associated transistor free of polysilicon emitter

A technology of coupled-gate transistors and emitters, which is applied in the manufacture of transistors, semiconductor devices, semiconductor/solid-state devices, etc., can solve problems such as secondary breakdown, high temperature, and high current density, and achieve low dynamic power consumption and high tube temperature. Low, good consistency

Inactive Publication Date: 2017-07-04
李思敏
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The collector-emitter current passes through the narrow emitter area concentratedly, the current density under the

Method used

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  • Gate associated transistor free of polysilicon emitter
  • Gate associated transistor free of polysilicon emitter
  • Gate associated transistor free of polysilicon emitter

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Embodiment Construction

[0042] The invention relates to a connected-gate transistor without a polysilicon emitter and a manufacturing method thereof.

[0043] Figure 1 to Figure 5 It is a structural schematic diagram of an embodiment of a connected-gate transistor without a polysilicon emitter and a process flow diagram along the A-A section of the present invention. The shown structure includes an N-type low-resistivity layer 42 in the lower layer and an N-type high-resistivity layer in the upper layer. The upper surface of the silicon substrate sheet 4 of the rate layer 41 has an N-type emitter region 3 with a high doping concentration. Region 2, the side of the P-type base region 2 is connected to the P-type concentrated base region 6 with a higher doping concentration than the P-type base region 2, the P-type concentrated base region 6 is orthogonal to the bus bar 61 in the P-type concentrated base region, and the silicon lining There is a base metal layer 10 above the bottom sheet 4, and the u...

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Abstract

The invention relates to a gate associated transistor free of a polysilicon emitter. An N type high-doping-concentration emitter region is arranged on the upper surface of a silicon substrate sheet, wherein an N type low-electrical-resistivity layer is on the lower layer while an N type high-electrical-resistivity layer is on the upper layer of the silicon substrate sheet; the upper surface of the emitter region is connected with an emitter metal layer; the gate associated transistor is characterized in that a base electrode metal layer is connected with the upper surface of a concentration base region bus bar; and the upper surface of a concentration base region is connected with the emitter region. The gate associated transistor has the advantages of capability of providing more uniform current distribution, relatively high impact resistance, higher consistency and lower cost.

Description

technical field [0001] The invention belongs to the technical field of silicon semiconductor devices, and relates to a connected-gate transistor, in particular to a connected-gate transistor without a polysilicon emitter. Background technique [0002] In 1979, Hisao Kondo proposed the gate associated transistor GAT (Gate Associated Transistor), followed by a detailed analysis (see IEEE Trans. Electron Device, vol. ED-27, PP.373-379.1980). In 1994, Chen Fuyuan, Jin Wenxin, and Wu Zhonglong made a further analysis of the gate transistor GAT (see "Power Electronics Technology", No. 4, 1994, 1994.11.pp52-55), pointing out that the gate transistor device exhibits high withstand voltage, Excellent characteristics such as fast switching and low saturation voltage drop. [0003] The combined gate transistor is a compound transistor of a bipolar transistor and an electrostatic induction transistor, and is a special bipolar transistor. Tie-gate transistors are also called electrosta...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L21/336H01L29/80
CPCH01L29/0615H01L29/0638H01L29/0646H01L29/66409H01L29/80
Inventor 李思敏
Owner 李思敏
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